PCIe DPU Storage Access via Processor Cache Queues
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Solution Overview
Problem
Existing data storage technologies require host-side processors to access storage devices, occupying valuable computing resources and increasing hardware design complexity when a Data Processing Unit (DPU) is connected via hardware cables.
Innovation Solution
A data access method using a DPU that writes access requests to a processor's cache queue and sends instructions in PCIe point-to-point transmission mode to storage devices, allowing direct access without hardware cables, thus reducing resource occupation and design complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the host-side processor accesses the storage device directly, then data storage can be completed, but processor resources are occupied and computing efficiency decreases
Solution Approach 1:
The patent extracts the data storage function from the host-side processor by introducing a DPU that can independently access storage devices. The DPU is configured with storage access capabilities and can handle storage I/O tasks without involving the host processor, thereby freeing processor resources for computing tasks and improving overall system productivity.
2Productivity
If a hardware cable connection is added to connect the DPU to the storage device, then the DPU can access the storage device directly, but hardware design complexity increases
Solution Approach 1:
The patent makes the host-side processor serve multiple functions: it acts as both the computing processor and as a storage access controller. The processor is configured with a storage access module that can generate and send storage access instructions to storage devices, and includes cache queues for buffering access requests. This multi-functionality eliminates the need for separate hardware cable connections between DPU and storage devices, reducing hardware complexity while maintaining storage access efficiency.
3Productivity
If the DPU is disposed outside the host, then the processor can focus on computing tasks, but hardware connection complexity increases
Solution Approach 1:
The patent introduces the host-side processor as an intermediary between the DPU and storage devices. The processor's storage access module acts as a mediator that receives storage access requests from the DPU, generates appropriate access instructions, buffers them in cache queues, and sends them to storage devices. This intermediary approach allows the DPU to be disposed outside the host while avoiding complex direct hardware connections to storage devices.
Data Source
AI summary
After writing an access request into a first cache queue of a processor, a data processing unit (DPU) sends, in a Peripheral Component Interconnect Express (PCIe) point-to-point transmission mode, a first instruction to a storage device to which an identifier of the storage device points, where the first instruction instructs the storage device to obtain the access request from the first cache queue and execute the access request. The access request includes the identifier of the storage device to be accessed, and the storage device is connected to the processor and not directly connected to the DPU. The first instruction includes location information of the access request in the first cache queue.