PCIe Endpoint Boot From Root Complex Memory With Minimal Local RAM

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Solution Overview

Problem

The existing method of transferring boot software from a root complex to a PCIe endpoint's volatile memory for execution results in increased complexity and cost due to the need for large memory storage and centralized management by the root complex.

Innovation Solution

The boot process is divided into two stages, where configuration software is executed locally to define an endpoint configuration block, and boot software is fetched in portions from the root complex memory via PCIe bus, reducing the need for large local memory and enabling centralized management by the root complex.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If boot software is transferred to PCIe endpoint's volatile memory for execution, then the endpoint can execute boot software independently, but memory requirements and system complexity increase

Engineering Contradiction:
Improveindependent execution capabilityVSAvoidmemory management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the boot process into two distinct stages: configuration stage (executing configuration software stored locally in non-volatile memory) and boot stage (fetching and executing boot software from root complex memory). This segmentation allows the endpoint to have minimal local memory while still achieving independent execution capability, resolving the contradiction between reliability and complexity.

Inventive Principle:
Principle #1Segmentation

2Speed

If boot software is stored in PCIe endpoint's volatile memory, then execution speed improves, but memory cost and size requirements increase

Engineering Contradiction:
Improveboot software execution speedVSAvoidmemory size requirement
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent applies preliminary action by having the root complex prepare and stage the boot software in its own memory before the endpoint needs to execute it. The endpoint configuration block is pre-configured with the memory address where boot software will be located, allowing the endpoint to directly fetch and execute boot software from root complex memory without requiring large local volatile memory, thus achieving fast execution with minimal memory requirements.

Inventive Principle:
Principle #10Preliminary action

3Ease of operation

If boot software is managed centrally by root complex, then management simplicity improves, but transfer and access complexity increases

Engineering Contradiction:
Improvesoftware management simplicityVSAvoidtransfer protocol complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent introduces the endpoint configuration block (ECB) as an intermediary structure that bridges the root complex and endpoint. The ECB contains critical information including the memory address of boot software, allowing the root complex to manage boot software centrally while providing the endpoint with direct access information. This intermediary approach simplifies management while avoiding complex transfer protocols by using standard PCIe memory access operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20260079718A1System and method to boot a pcie endpoint from boot software stored in memory of a pcie root complex
Publication Date: 2026.03.19 NXP BV
  • US20260079718A1 patent drawing
  • US20260079718A1 patent drawing
  • US20260079718A1 patent drawing

AI summary

Boot of a PCIe EP coupled to a RC by a PCIe bus comprises setting, by the PCIe EP, a program counter of a CPU of the PCIe EP to an address indicative of an address of memory of the RC which stores the boot software to execute. A memory transaction to read, by the PCIe EP via the PCIe bus, a portion of the boot software stored in the address of the memory of the RC which store the boot software is performed followed by receiving by the CPU the portion which is read from the memory of the RC via the PCIe bus and PCIe controller of the EP. The portion is stored by the CPU in an instruction cache of the CPU and the CPU of the PCIe EP executes an instruction of the portion of the boot software that is received.