PCIe Endpoint Bandwidth via Dual Link Segmentation
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Solution Overview
Problem
The PCIe bandwidth available to endpoint devices in computer systems is limited, particularly for graphics applications using turbo cache technology, where the PCIe link becomes a bottleneck, restricting bus throughput efficiency.
Innovation Solution
A computer system configuration with first and second controllers and an endpoint device connected through first and second PCIe links, allowing the endpoint device to utilize increased bandwidth by sending read requests over multiple PCIe links and receiving ordered read completion packets, thereby enhancing PCIe bus throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single PCIe link is used to connect endpoint device to controllers, then device complexity is reduced, but PCIe bandwidth is limited causing bottleneck in graphics applications
Solution Approach 1:
The system segments the PCIe communication path by implementing multiple PCIe links (first PCIe link and second PCIe link) between the endpoint device and controllers. This allows bandwidth segmentation where different data streams can be transmitted simultaneously over separate physical links, thereby increasing total available bandwidth without requiring a single complex high-speed link.
Solution Approach 2:
The invention transitions from a single-dimension PCIe connection to a multi-dimensional architecture by adding spatial redundancy through multiple PCIe links. This dimensional expansion allows parallel data transmission paths, effectively multiplying the bandwidth capacity while distributing the complexity across separate manageable links rather than concentrating it in one link.
2Quantity of substance
If read requests are sent over multiple PCIe links to increase bandwidth, then PCIe bandwidth is increased, but maintaining proper ordering of read completion packets becomes more difficult
Solution Approach 1:
The system implements feedback mechanisms where the endpoint device monitors and tracks the status of read requests sent over multiple PCIe links. By maintaining state information about outstanding requests and their expected order, the system can properly reorder or buffer read completion packets to ensure correct sequencing, thus maintaining reliability while utilizing multiple links for increased bandwidth.
Solution Approach 2:
The invention applies preliminary action by pre-establishing tracking and buffering structures at the endpoint device before read requests are dispatched over multiple PCIe links. This allows the system to anticipate and manage the ordering requirements of completion packets in advance, ensuring that even though packets may arrive out of order from different links, they can be correctly sequenced without compromising data integrity.
Data Source
AI summary
In a computer system employing PCI Express (PCIe) links, the PCIe bandwidth is increased by configuring an endpoint device with at least two PCIe interfaces, and coupling the first of these interfaces with a PCIe interface of a system controller and the second of these PCIe interfaces with an expansion PCIe interface of an I/O controller. Therefore, the endpoint device's performance becomes more efficient. For example, if the endpoint device is a graphics processing unit, then the endpoint device can execute more frames per second. When a read request is split up and issued as multiple read requests over the at least two PCIe interfaces, the multiple read completion packets that are received in response thereto are ordered in accordance with the timing of the multiple read requests.