PCIe Endpoint Isolation for Link Retention During SoC Warm Reset
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Solution Overview
Problem
Existing computing systems face instability and performance degradation during frequent device resets due to the interruption of PCIe links, particularly in server and virtual computing environments where hundreds or thousands of client instances require device resets, leading to significant downtime and impact on server performance.
Innovation Solution
The PCIe endpoint of a device is disconnected from the System on a Chip (SoC) during the reset process, maintaining the link independently, and is reconnected after the SoC reset is complete, ensuring the PCIe link remains active and unaffected by the SoC reset.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the PCIe link is disconnected during device reset, then the SoC can be reset completely, but the link stability deteriorates and re-initialization is required
Solution Approach 1:
The device is segmented into two independent parts: the endpoint which maintains the PCIe link, and the SoC which undergoes reset. The reset controller disconnects the endpoint from the SoC internally while keeping the external PCIe link active, allowing independent reset of the SoC without affecting link stability.
Solution Approach 2:
The reset controller acts as an intermediary between the endpoint and SoC during reset operations. It manages the disconnection and reconnection of the endpoint from the SoC while maintaining the external PCIe link, coordinating the reset sequence to prevent link interruption.
2Productivity
If the PCIe link is maintained active during reset, then downtime is reduced, but the reset process becomes more complex
Solution Approach 1:
The connection topology is made dynamic through the reset controller, which can switch the endpoint connection between the SoC and a bypass path. During normal operation, the endpoint connects to the SoC; during reset, the controller dynamically reconfigures the connection to maintain the PCIe link while isolating the SoC for reset.
3Adaptability or versatility
If frequent device resets are performed, then client instances can be rapidly deployed, but link instability accumulates and performance degrades
Solution Approach 1:
The system prepares for frequent resets by establishing a protected PCIe link path beforehand. The reset controller pre-configures the bypass path and ensures the endpoint can maintain link connectivity before, during, and after reset operations, cushioning against the cumulative effects of frequent resets on link stability.
Data Source
AI summary
A warm reset of a device is described with retention of a link with the device. In an example, an endpoint of a device is configured to maintain a link to another node and to receive a reset command. A reset controller is configured to disconnect the endpoint of the device from a system-on-a-chip (SoC) of the device, to command a reset of the SoC after the disconnecting the endpoint, and to connect the endpoint to the SoC after the reset has been performed.