PCIe Endpoint Polling Mechanism for DMA Data Transfer Latency
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Solution Overview
Problem
PCIe-based data transmission faces challenges with high latency and low bandwidth, especially when handling large payloads, and increased CPU overhead due to frequent interrupt signals and DMA controller initialization.
Innovation Solution
A method and apparatus that involve polling a DMA controller to read data from a root complex memory, determining data availability through a doorbell message, and optimizing data packet lengths to improve transmission efficiency by reducing unnecessary polling and cache operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data packets with large payloads are transmitted on a PCIe bus, then transmission bandwidth is maintained but transmission latency increases
Solution Approach 1:
The patent segments the data transmission process into multiple stages: doorbell message notification, polling phase initiation, data reading by DMA controller, and completion notification. This segmentation allows the system to maintain high bandwidth for large payloads while reducing overall latency through parallel processing and optimized state transitions.
Solution Approach 2:
The patent implements dynamic polling mechanisms where the endpoint device adjusts its polling behavior based on the state of data transmission. The processor transitions between different polling phases (initial polling, continuous polling, and stopped polling) to optimize both bandwidth utilization and latency reduction adaptively.
2Productivity
If data packets with small payloads are transmitted, then bandwidth utilization decreases but CPU overhead increases due to interrupt signals
Solution Approach 1:
The patent implements a self-service mechanism where the endpoint device autonomously manages its polling operations through doorbell message notifications. The device can independently determine when to start and stop polling based on received notifications, reducing the need for CPU intervention and interrupt handling for small payload transmissions.
Solution Approach 2:
The patent employs feedback mechanisms through doorbell messages that notify the endpoint device of data availability. This feedback loop allows the system to optimize polling behavior dynamically, reducing CPU overhead by eliminating unnecessary polling operations when no data is available, particularly beneficial for small payload scenarios.
3Speed
If frequent polling is performed to check data availability, then data transmission speed improves but CPU overhead increases
Solution Approach 1:
The patent implements periodic polling actions triggered by doorbell message notifications rather than continuous polling. The endpoint device performs polling at specific intervals determined by received notifications, maintaining fast data transmission speed while significantly reducing CPU overhead by eliminating redundant polling operations.
Solution Approach 2:
The patent performs preliminary actions by sending doorbell messages to notify the endpoint device of data availability before actual data transmission begins. This preliminary notification allows the system to prepare for efficient polling operations, ensuring fast data retrieval while minimizing unnecessary CPU involvement by only initiating polling when data is actually available.
Data Source
AI summary
A method and apparatus for transmitting data based on peripheral component interconnect express (PCIe) are disclosed. The method includes receiving, at an endpoint (EP), a doorbell (DB) message transmitted from a root complex (RC) via a PCIe connection between the endpoint (EP) and the RC; based on the DB message, transmitting, by polling of a processor of the EP, a read request message to a direct memory access (DMA) controller of the EP; and in response to reception of the read request message by the DMA controller, reading, by the DMA controller, data to be transmitted from a memory of the RC and recording read data into a memory of the EP.