Error Correlation Logging for PCIe Bus Error Correction
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Solution Overview
Problem
As serial interconnects, such as PCIe, experience increased data rates, maintaining a bit error rate (BER) of 10^-12 or better becomes difficult due to cross-talk, inter-symbol interference, and channel loss, leading to correlated burst errors across lanes, which conventional error correction methods struggle to address effectively.
Innovation Solution
The implementation of mechanisms and logic circuitry to detect and correct error bursts across lanes, utilizing different Forward Error Correction (FEC) codes and Cyclic Redundancy Check (CRC) mechanisms, along with error logging and retimer configurations, to tune error correction based on error correlation patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data rate for serial links is increased beyond 32.0 GT/s, then bandwidth and transmission speed are improved, but bit error rate deteriorates due to cross-talk, inter-symbol interference, and channel loss
Solution Approach 1:
The patent employs PAM-4 modulation which changes the signal encoding parameter from traditional NRZ to pulse amplitude modulation with 4 levels, allowing higher data rates while managing error rates through the inherent error correction capabilities of the modulation scheme
Solution Approach 2:
The patent implements feedback mechanisms where error information is logged and analyzed to dynamically adjust error correction strategies, enabling the system to adapt to changing channel conditions and maintain reliability at higher data rates
2Reliability
If conventional error correction methods are used, then error detection capability is provided, but correlated burst errors across lanes cannot be effectively addressed
Solution Approach 1:
The patent implements dynamic error correction where the system continuously monitors error patterns and adapts its correction strategy in real-time, switching between different FEC codes and correction intensities based on the observed error correlation characteristics
Solution Approach 2:
The patent segments the error correction approach by implementing lane-specific error logging and correction, allowing each lane to be treated independently with tailored correction strategies rather than applying a uniform correction method across all lanes
3Reliability
If error logging and dynamic adjustment mechanisms are implemented, then error correction effectiveness is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service error correction where the system automatically logs errors, analyzes patterns, and adjusts correction strategies without external intervention, reducing the need for complex external control mechanisms while maintaining high error correction effectiveness
Data Source
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AI summary
Systems and devices can include forward error correction (FEC) logic to identify a correctable error in the first flit, and correct the correctable error using three error correcting code (ECC) groups. System and devices can also include an error log, the correctable error log to log a symbol number in the first flit corrected by each ECC group, and to log a magnitude of the correctable error corrected by each ECC group in the first flit; and a configuration register to log link error correlation, the link error correlation comprising a indication of one or more bits in error in the first flit.