PCIe Error Logging via Fixed Queue Depth
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing Input/Output (I/O) subsystems face challenges in error logging due to dependency on clock frequency ratios, which complicates the independent logging of uncorrectable errors across different clock domains in PCIe systems.
Innovation Solution
Implementing an error logging mechanism with a fixed queue depth of two, independent of clock frequencies, that stores and logs 128-bit Transaction Layer Packet headers and First Error Pointers, enabling clock-crossing from the source to the destination clock domain, thus maintaining error logging independence from clock frequency ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error logging is implemented in traditional I/O subsystems, then error detection capability is improved, but the system becomes dependent on clock frequency ratios which complicates independent logging across different clock domains
Solution Approach 1:
The patent introduces an intermediary mechanism - a buffer storage structure that decouples the error logging function from the clock frequency ratio constraints. This buffer acts as a mediator between the error detection logic and the configuration register, allowing errors to be logged independently of clock domain synchronization requirements. The buffer stores error information temporarily, enabling reliable error detection without being constrained by clock frequency relationships.
2Adaptability or versatility
If clock domain crossing is implemented for error logging, then independence from clock frequency ratios is achieved, but the mechanism for storing and transferring error information becomes more complex
Solution Approach 1:
The patent segments the error logging function into distinct components: error detection logic, buffer storage structure, and configuration register. This segmentation allows each component to operate independently with respect to clock domains. The buffer storage is divided into multiple entries (at least two) to handle clock domain crossing, enabling the system to achieve clock frequency independence while managing complexity through modular design.
Solution Approach 2:
The patent introduces a temporal dimension to error logging by implementing a buffer that stores error information across different time frames corresponding to different clock domains. Instead of attempting synchronous logging across clock domains, the system logs errors in the source clock domain's time frame and transfers them to the destination clock domain, effectively adding a time-based dimension to resolve clock frequency ratio dependencies.
3Adaptability or versatility
If a fixed queue depth of two is used for error logging, then clock frequency ratio independence is achieved, but the queue capacity is limited
Solution Approach 1:
The patent implements a wraparound buffer mechanism where the fixed queue of depth two discards older error entries when full and recovers storage space by overwriting or wrapping around to the beginning. This allows the limited queue capacity to effectively handle continuous error logging across clock domains by periodically discarding and recovering storage positions, maintaining clock frequency independence while managing limited storage capacity.
Data Source
AI summary
A method and system for error logging that is independent of the clock frequency ratio in an I/O subsystem. In one embodiment of the invention, the I/O subsystem has an error logging mechanism with a fixed queue depth of two and is independent of the clock frequencies in the I/O subsystem. The I/O subsystem has two queue entries for storing or logging the uncorrectable errors. In one embodiment of the invention, the I/O subsystem has two queue entries for storing or logging the 128-bit TLP Header and the First Error Pointer (FEP) of the uncorrectable errors detected in the I/O subsystem.