PCIe Fabric Buffer for Virtual Memory Sharing

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Solution Overview

Problem

Existing methods for sharing memory spaces among information processing devices, such as RDMA and NTB, face limitations in connectivity, access restrictions, and configuration dependencies, preventing seamless memory sharing across different devices, especially in non-cluster configurations.

Innovation Solution

A communication device with a serial interface compliant with the PCIe standard, a requester unit, a fabric communication unit, and a completer unit, which converts packets to enable memory sharing among devices connected via a fabric using unique device identifiers, allowing virtual extension of memory spaces and dynamic access management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If RDMA is used to share memory space among information processing devices, then memory sharing capability is improved, but processing overhead increases because each device individually manages the memory space

Engineering Contradiction:
Improvememory sharing capabilityVSAvoidprocessing overhead
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces a buffer device as an intermediary between information processing devices to manage memory space. The buffer device receives write requests from one device and forwards them to the target device, eliminating the need for individual memory management at each device. This mediator approach reduces processing overhead while maintaining memory sharing capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If NTB is used to directly access memory space of another information processing device, then access speed is improved, but a limitation of 64 bits is imposed because the access is based on PCIe Express

Engineering Contradiction:
Improvememory access speedVSAvoidaddressable memory range
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

The patent extends the address space by introducing a buffer device that handles address translation and forwarding. Instead of being constrained by the 64-bit PCIe address limit, the system uses the buffer device to manage addresses beyond this limit, effectively adding another dimension to the addressable memory space while maintaining direct access capabilities.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If PTL 1 method is used to transfer data between clusters, then data transfer efficiency is improved by avoiding buffer copying, but it is impossible to connect a completely different information processing device in a non-cluster configuration

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoiddevice connectivity flexibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent creates a universal buffer device that can handle both cluster and non-cluster configurations. The buffer device receives packets from any information processing device connected via fabric, performs address translation, and forwards them appropriately. This multi-functional approach maintains high data transfer efficiency while enabling connectivity across different device types and configurations.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Adaptability or versatility

If PTL 2 system is used to provide virtual shared memory on network, then memory sharing is enabled, but a shared memory is divided based on pages and any single device is allowed to have access to each page

Engineering Contradiction:
Improvememory sharing capabilityVSAvoidaccess restriction complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent extracts the page-based access restriction mechanism from the memory sharing system. By using a buffer device to manage address translation and forwarding, the system removes the limitation that prevents multiple devices from accessing the same memory pages simultaneously. This extraction of the restrictive mechanism enables true shared memory access while maintaining virtual memory capabilities.

Inventive Principle:
Principle #2Taking out (Extraction)

5Ease of operation

If PTL 3 method is used for multiprocessor system memory access, then memory access is enabled, but devices need to have an identical and fixed configuration because the access destination is determined based on a memory address

Engineering Contradiction:
Improvememory access capabilityVSAvoiddevice configuration flexibility
Core Design Contradiction:
Ease of operationVSAdaptability or versatility

Solution Approach 1:

The patent introduces dynamic address translation through the buffer device. Instead of using fixed memory addresses that require identical device configurations, the buffer device dynamically translates addresses based on the actual device identities and current system state. This dynamic approach maintains ease of memory access while enabling flexible device configurations and arbitrary device connections.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11836105B2Communication device, information processing system, and communication method
Publication Date: 2023.12.05 NEC CORP
  • US11836105B2 patent drawing
  • US11836105B2 patent drawing
  • US11836105B2 patent drawing

AI summary

A communication device mounted in each of a plurality of information processing devices connected to a fabric, the communication device comprises: a serial interface that transmits and receives a first packet compliant with a Peripheral Component Interconnect Express (PCIe) standard; a requester unit that acquires the first packet from the serial interface and converts the first packet that has been acquired into a second packet that is transmitted and received via the fabric among a plurality of the information processing devices sharing a memory space that is virtually extended by using a device identifier specific to each of the information processing devices; a fabric communication unit that transmits and receives the second packet via the fabric; and a completer unit that acquires the second packet from the fabric communication unit and generating a response packet to a request included in the second packet that has been acquired.