PCIe FLIT Mode L0ps Link State Power Management
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Solution Overview
Problem
The Peripheral Component Interconnect Express (PCIe) link in FLIT mode lacks a power-saving state without going through a recovery state, limiting power efficiency during low traffic conditions, as the standby state L0s is not available, and transitioning to L1 requires a handshake sequence.
Innovation Solution
Introducing a new link state, L0ps, which allows PCIe links to enter a low-power standby state independently from L0p in FLIT mode, enabling lanes to transition without handshaking and quickly recover without going through a recovery state, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If PCIe link transitions to L1 standby state, then power consumption is reduced, but handshake sequence is required increasing transition time
Solution Approach 1:
The patent segments the link into RX and TX line pairs that can independently transition between states. Each line pair can enter L0ps standby state independently without requiring coordinated handshake sequences, allowing parallel power-saving transitions and reducing overall transition time.
Solution Approach 2:
The patent introduces dynamic state management where link width can change during operation and lines can transition to different states independently. The L0ps state enables dynamic power management by allowing individual line pairs to enter standby based on their specific traffic conditions without global coordination overhead.
2Productivity
If all lanes are kept active for data traffic, then data transfer capability is maintained, but power consumption increases during low traffic conditions
Solution Approach 1:
The patent divides the link into multiple independently controllable line pairs (RX and TX). During low traffic conditions, individual line pairs can transition to L0ps standby state while others remain active, allowing the system to maintain necessary data transfer capability while reducing overall power consumption by segmenting power management across individual lines.
Solution Approach 2:
Different line pairs within the same link can have different operational states simultaneously. Some line pairs may remain active to maintain data transfer capability while other line pairs enter standby state to reduce power consumption, based on their specific traffic demands and link width requirements.
Data Source
AI summary
A new peripheral component interconnect express (PCIe) link state can enhance power saving capabilities of a PCIe link operating in a flow control unit (FLIT) mode. A device can operate a data link with a host in a FLIT mode using fixed-sized packets, the data link being in a partial width link state (PLS) in which a first set of lanes of the data link are in an electrical idle state and a second set of lanes of the data link are in an active state available for data traffic with the host. The device can transition one or more lines of the second set of lanes from the PLS to a partial width standby link state (PSLS) in which the one or more lines of the second set of lanes are in a standby state that has lower power consumption than the active state.