PCIe Flow Control Credit Allocation via OS Processor Affinity
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Solution Overview
Problem
High-performance PCIe devices face latency and bandwidth issues due to insufficient buffering capacity in intermediate components, particularly when performing bus mastering and point-to-point transactions across high-capacity interconnects like PCIe and QPI, especially in high-end systems with extensive I/O operations.
Innovation Solution
The allocation of guaranteed flow control credits for PCIe devices is ensured through OS or VMM feedback based on processor thread affinity, with the OS/VMM communicating processor affinity to the platform chipset to configure additional buffering across the entire path, including coherent interconnects like QPI and MPL, using software applications and Quality of Service policies to determine the necessary credits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If intermediate components use standard buffering capacity, then device complexity is reduced, but latency increases for high-performance PCIe devices
Solution Approach 1:
The patent applies local quality by allocating different buffering capacities to different intermediate components based on their specific roles and the performance requirements of connected devices. High-performance PCIe devices receive guaranteed flow control credits and dedicated buffering resources, while other components use standard buffering. This selective allocation reduces latency for critical paths without unnecessarily increasing complexity across the entire system.
2Loss of time
If guaranteed flow control credits are allocated to high-performance PCIe devices, then latency is reduced, but device complexity increases
Solution Approach 1:
The patent implements preliminary action by pre-allocating guaranteed flow control credits to high-performance PCIe devices during system initialization or configuration. This advance allocation ensures that when these devices perform bus mastering or point-to-point transactions, they immediately have the buffering resources available, eliminating the need for dynamic resource negotiation and reducing transaction latency without adding complex runtime control mechanisms.
3Reliability
If additional buffering is configured across the entire communication path, then bandwidth reliability is improved, but device complexity increases
Solution Approach 1:
The patent uses an intermediary approach by introducing a flow control credit allocation mechanism that mediates between high-performance PCIe devices and intermediate components. The system configures guaranteed credits at specific intermediary points (Root Complexes, PCIe switches) that are strategically positioned to provide buffering where most needed. This targeted intermediary buffering improves bandwidth reliability for critical transactions without requiring additional buffering at every component in the path, thus limiting the increase in overall system complexity.
Data Source
AI summary
Methods and apparatus relating to allocation of flow control credits for high performance devices are described. In some embodiments, controls and/or configuration structures may be provided for the OS (Operating System) or VMM (Virtual Machine Manager) to indicate possible processor affinity (e.g., of a device driver for a given PCIe device) to the platform components (in a platform dependent fashion, for example). Using this data, the platform components could configure the RC (Root Complex) ports and/or intermediate components (such as switches, bridges, etc.) to pre-allocate buffers for the links coupling the PCIe device to the RC ports or intermediate components. Other embodiments are also disclosed and claimed.