PCIe FLR Reset Handling with DMA Drain and Drop Control
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Solution Overview
Problem
Current NVMe technologies face challenges in efficiently handling reset scenarios and verify commands, leading to hindered latency and bandwidth due to the need for stopping all transfers or CPU calculations, which can prolong reset times and impact performance.
Innovation Solution
The implementation of a controller with a direct memory access (DMA) unit and a drain unit or drain and drop unit between the DMA and the PCIe bus, which prevents transactions associated with FLR commands from passing to the MAC during execution, allowing requests to be stored, removed, and responded to without delivery to the MAC, and provides successful or unsuccessful completion messages based on command outcomes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FLR command is executed to reset the controller, then the controller can recover from error states and maintain reliability, but the timing constraint of 100mSec is extended due to pending transactions blocking the reset
Solution Approach 1:
The patent segments the data path by introducing a drain unit between the DMA unit and MAC that separates FLR-related transactions from other transactions. This segmentation allows the drain unit to selectively block only FLR-related transactions during reset while allowing other transactions to proceed, thus reducing the reset timing constraint extension.
Solution Approach 2:
The drain unit acts as an intermediary component between the DMA unit and MAC. It receives transactions from the DMA unit, identifies FLR-related transactions, and selectively blocks them during reset operations. This intermediary mechanism enables the controller to manage reset timing constraints more effectively by preventing specific transactions from blocking the reset process.
2Reliability
If verify command is executed to check data integrity, then data protection is ensured, but latency and bandwidth are hindered due to stopped transfers or CPU calculation
Solution Approach 1:
The drain unit enables the system to perform self-service by automatically handling verify commands and end-to-end protection without requiring CPU intervention. The drain unit monitors transactions, identifies verify commands, and manages them autonomously, eliminating the need for CPU-based verification and reducing latency.
Solution Approach 2:
The patent replaces the traditional CPU-based verification mechanism with a hardware-based drain unit that handles verify commands and protection calculations automatically. This substitution of mechanical (CPU) processing with hardware-based automation reduces verification time and improves bandwidth utilization.
3Reliability
If all transfers are stopped during reset or verify operations, then data integrity can be maintained, but overall system productivity decreases due to halted operations
Solution Approach 1:
The drain unit applies local quality by selectively blocking only FLR-related transactions during reset operations while allowing other transactions to continue uninterrupted. This localized blocking approach maintains data protection for critical operations while preserving overall system throughput and productivity.
Solution Approach 2:
Instead of stopping all transfers during reset or verify operations, the drain unit implements partial action by blocking only the necessary FLR-related transactions. This selective blocking reduces the impact on system productivity while still ensuring data integrity for the affected operations.
Data Source
AI summary
The controller is configured to receive commands from a host device through a PCIe bus having a MAC, send data to the host device through the PCIe bus, and execute a function level reset (FLR) command. The controller includes a direct memory access (DMA) unit and either a drain unit or a drain and drop unit coupled between the DMA and the PCIe bus. The units are configured to prevent transactions associated with the FLR command to pass from the DMA to the MAC during execution of the FLR command, where the preventing transactions comprises receiving a request from the DMA, storing the request in a pipe, removing the request from the pipe, and providing a response to the DMA without delivering the request to the MAC. The drain and drop unit is configured to drop a MAC generated response.