PCIe Bus Transaction Ordering via CPU Flush Command
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Solution Overview
Problem
Current methods for data transfer between peripheral devices in computer systems, such as NIC and GPU, often require CPU intervention to verify transaction completion, leading to delays and overheads, even with direct peer-to-peer communication over PCIe buses.
Innovation Solution
A method involving two commands from the CPU to ensure data integrity and processing: the first command writes data in a bus transaction, and the second command executes a subsequent transaction to flush the data, allowing the peripheral device to process it without CPU intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If direct peer-to-peer data transfer between peripheral devices is implemented over PCIe bus, then data transfer speed and efficiency are improved, but transaction ordering issues cause data integrity problems
Solution Approach 1:
The patent applies preliminary action by having the CPU issue a flush command before the data transfer is complete. This flush command预先 establishes the ordering rule that all subsequent transfers must wait for its completion, ensuring data integrity is maintained from the outset rather than being verified afterward.
Solution Approach 2:
The flush command acts as an intermediary mechanism between the CPU and the PCIe bus transactions. It mediates the ordering of transactions by inserting a synchronization point that forces the bus to complete all pending transfers before allowing new ones, thus resolving the ordering conflict without CPU intervention in each transfer.
2Reliability
If CPU intervention is used to verify transaction completion, then data integrity is ensured, but system overhead and delay increase
Solution Approach 1:
The patent extracts the transaction verification function from the CPU by implementing an autonomous flush command mechanism. The CPU issues the flush command once and then continues executing other tasks without needing to wait for or verify each individual transaction completion, as the flush command autonomously manages the ordering and completion notification.
Solution Approach 2:
The flush command implements self-service by automatically managing the transaction ordering and completion verification without requiring CPU intervention. The PCIe bus and peripheral devices handle the ordering and completion notification autonomously based on the flush command, freeing the CPU from continuous verification tasks.
3Productivity
If relaxed ordering is enabled for enhanced DMA performance, then data transfer efficiency is improved, but transaction ordering guarantees are lost
Solution Approach 1:
The patent segments the data transfer process into two distinct phases: a flush command phase that establishes ordering guarantees, and subsequent relaxed ordering transfers that optimize performance. This segmentation allows the system to enjoy the benefits of relaxed ordering for bulk transfers while maintaining ordering integrity for critical synchronization points.
Solution Approach 2:
The flush command serves as a preliminary action that establishes the ordering framework before relaxed ordering transfers occur. By setting up the ordering guarantees upfront with the flush command, the system can then safely use relaxed ordering for subsequent transfers without compromising data integrity.
Data Source
AI summary
A method for computing includes submitting a first command from a central processing unit (CPU) to a first peripheral device in a computer to write data in a first bus transaction over a peripheral component bus in the computer to a second peripheral device in the computer. A second command is submitted from the CPU to one of the first and second peripheral devices to execute a second bus transaction, subsequent to the first bus transaction, that will flush the data from the peripheral component bus to the second peripheral device. The first and second bus transactions are executed in response to the first and second commands. Following completion of the second bus transaction, the second peripheral device processes the written data in.