PCIe Hardware Timestamping for Clock Synchronization
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Solution Overview
Problem
Current systems fail to achieve precise time synchronization between devices connected through PCIe or derived architectures due to non-deterministic communication delays, which affects the accuracy of applications like multichannel audio and requires software support, less desirable than a hardware solution.
Innovation Solution
A hardware mechanism that utilizes modified framing of PCIe packets to synchronize time between devices, including a method of transmitting and receiving time synchronization packets with a header to identify them, enabling precise time control across networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software mechanisms are used for time synchronization across networks, then implementation flexibility is improved, but synchronization precision deteriorates due to non-deterministic communication delays
Solution Approach 1:
The patent replaces software-based time synchronization mechanisms with a hardware-based solution using PCIe hardware counters and timestamping. The hardware counter directly timestamps packets at the physical layer, eliminating software intervention and non-deterministic delays. This substitution of mechanical/software system with hardware system resolves the contradiction by achieving both precision and flexibility through dedicated hardware time synchronization blocks.
Solution Approach 2:
The patent introduces a hardware intermediary component - the hardware counter - that sits between the network interface and the processing system. This intermediary directly timestamps packets before they enter the software processing pipeline, providing precise timing information without subjecting it to software scheduling uncertainties. The hardware counter acts as a mediator that bridges the gap between network timing and system processing timing.
2Measurement precision
If hardware-based time synchronization is implemented, then synchronization precision is improved, but device complexity increases
Solution Approach 1:
The patent makes the hardware counter multi-functional by using it for both time synchronization and packet timestamping. The same hardware counter that provides precise timing for synchronization also stamps packets with their exact arrival times for processing. This universal use of a single hardware component achieves precise synchronization without proportionally increasing device complexity, as one counter serves multiple purposes.
Solution Approach 2:
The patent merges the time synchronization function with the packet timestamping function into a single hardware counter mechanism. Rather than implementing separate hardware blocks for synchronization and timing, the design combines these functions so that the hardware counter simultaneously provides sync signals and packet timestamps. This merging reduces overall hardware complexity while maintaining synchronization precision.
3Quantity of substance
If PCIe Transaction Layer Packets are used for communication, then data transmission capability is improved, but communication latency control deteriorates due to queuing delays
Solution Approach 1:
The patent applies preliminary action by having the hardware counter timestamp packets immediately upon arrival before they enter the PCIe transaction processing queue. This preliminary timing capture occurs at the earliest possible moment, before any queuing delays can occur. The timestamp is recorded in advance, allowing the system to later compensate for or ignore the variable queuing delays without affecting the accuracy of time synchronization.
Data Source
AI summary
A method and apparatus for synchronizing time between a master device and a target device arranged across a network, wherein the target device communicates to the master device through a PCIe interconnect includes transmitting a first message at a first time from the master device to the target device, the first message including a message indicator; and receiving a reply message at a subsequent time from the target device to the master device, the reply message including the message indicator.