PCIe Switch I2C Timeout Hard Reset via MOS Power Cycle
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Solution Overview
Problem
Existing storage systems lack an effective method for automatically resetting I2C devices without a reset switch, particularly in scenarios where I2C communication timeouts occur, leading to potential single points of failure and prolonged downtime.
Innovation Solution
A storage system configuration that includes a PCIe switch capable of performing I2C communication, an auxiliary apparatus with a MOS switch to control power supply, and a CPLD for managing status and executing hard resets, allowing for power resupply and reset of I2C devices when communication timeouts happen.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If I2C communication is used between PCIe switch and storing apparatus, then communication capability is improved, but timeout occurs when device becomes unresponsive
Solution Approach 1:
The system implements a feedback mechanism where the PCIe switch monitors I2C communication status and detects timeouts. When a timeout is detected, the system automatically triggers a hard reset sequence through the auxiliary apparatus, creating a closed-loop control system that responds to communication failures and restores functionality.
Solution Approach 2:
The auxiliary apparatus acts as an intermediary between the PCIe switch and the storing apparatus. It receives hard reset commands from the PCIe switch and executes power control through the MOS switch, serving as a mediator that enables remote reset functionality without requiring direct access to the storing apparatus reset circuitry.
2Ease of operation
If hardware reset switch is added to I2C device, then reset capability is improved, but device complexity increases
Solution Approach 1:
The auxiliary apparatus serves as an intermediary that provides reset functionality remotely. Instead of adding physical reset switches to each I2C device, the system uses the auxiliary apparatus to receive reset commands and control power supply through the MOS switch, thereby providing reset capability without increasing device complexity.
Solution Approach 2:
The invention replaces mechanical reset switches with an electronic control system. The hard reset command is transmitted electronically through the PCIe switch and auxiliary apparatus, which then controls the MOS switch to cut and restore power, substituting mechanical switch operations with electronic control mechanisms.
3Reliability
If power supply is stopped and resupplied for hard reset, then device reset is achieved, but downtime increases
Solution Approach 1:
The system performs preliminary detection of I2C communication timeouts and automatically triggers the hard reset sequence without requiring manual intervention. By detecting the timeout condition and initiating the power cycle automatically, the system minimizes the time the device remains non-functional by eliminating delays associated with manual detection and activation of reset procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the performance of hard resets for I2C devices without a reset switch, mitigating single points of failure and reducing downtime by ensuring power supply control and communication recovery through the MOS switch and CPLD management.
Implementation Method 1
a MOS switch that controls power supply from the power source to the storing apparatus
Data Source
AI summary
A storage system includes: a power source; a drive box that stores a storage apparatus; a storing apparatus having a storage unit in which data regarding devices is stored; a PCIe switch that can switch between a plurality of communication paths, has a communication path connected at least to the storage apparatus, and can further perform I2C communication with the storing apparatus; an auxiliary apparatus that can perform I2C communication with the PCIe switch; and a MOS switch that controls power supply from the power source to the storing apparatus, wherein if timeout of the I2C communication between the PCIe switch and the storing apparatus occurs, the PCIe switch transmits a hard reset command to the auxiliary apparatus; and wherein when the auxiliary apparatus receives the hard reset command, the auxiliary apparatus stops the power supply to the storing apparatus by using the MOS switch and then performs power resupply.