PCIe Interconnect via Network Switch for Low Latency Clustering
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Solution Overview
Problem
Current high-speed interconnect schemes, such as Ethernet with TCP/IP protocols, suffer from high latency and packet drop issues under high traffic, limiting the growth of distributed computing and storage systems, and require protocol changes or data encapsulation, which introduce delays and costs.
Innovation Solution
The PCI Express (PCIe) standard is used for direct, high-speed data transfer between PCIe-enabled systems through PCIe-based peripherals connected via network switches, eliminating intermediate protocol conversions and allowing scalable bandwidth without architectural changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If Ethernet connection with TCP/IP protocols is used for high-speed data transfer, then transport speeds from 10 MB to 10 GB/sec are achieved, but high overhead and inherent latency make it unsuitable for some distributed applications
Solution Approach 1:
The patent extracts and removes the TCP/IP protocol layer from the data transfer path, allowing raw Ethernet frames to be transmitted directly between PCIe devices. This eliminates protocol overhead and reduces latency while maintaining high transfer speeds, directly resolving the contradiction between speed and latency.
Solution Approach 2:
The patent introduces a PCIe bridge device as an intermediary that enables direct PCIe-to-Pcie communication over Ethernet infrastructure. This mediator translates PCIe transactions to Ethernet frames and back, allowing low-latency communication while utilizing existing Ethernet hardware, thus achieving both high speed and low latency.
2Ease of operation
If TCP/IP protocol is used for data transfer, then data can be transmitted between systems, but TCP/IP protocol tends to drop data packets under high traffic congestion which require resend and cause delays
Solution Approach 1:
The patent removes the TCP protocol layer that causes packet drops under congestion, using raw Ethernet frames instead. This eliminates TCP's flow control and retransmission mechanisms that lead to delays, providing more reliable and predictable data transfer for high-performance applications.
Solution Approach 2:
The patent changes the communication parameter from TCP/IP protocol to raw Ethernet frames, fundamentally altering how data is transmitted. This parameter change eliminates protocol-induced packet drops and retransmissions, improving reliability and reducing latency under high traffic conditions.
3Speed
If protocol changes or data encapsulation are made to achieve high-speed interconnect, then interconnect capability is improved, but associated delays increase and costs increase
Solution Approach 1:
The patent extracts and eliminates unnecessary protocol conversion and data encapsulation steps in the interconnect path. By using raw Ethernet frames directly between PCIe devices, it removes the delays associated with protocol processing while maintaining high interconnect speeds.
Solution Approach 2:
The PCIe bridge device performs self-service by directly translating PCIe transactions to Ethernet frames without requiring external protocol conversion. This self-contained approach eliminates additional processing delays and reduces system complexity, achieving high speed with minimal latency.
4Loss of time
If PCIe standard based peripheral are directly connected using PCIe standard based peripheral to PCIe standard based peripheral direct data link connections, then latencies of communication are reduced, but number of links per connection must be increased to meet bandwidth needs
Solution Approach 1:
The patent merges multiple PCIe links into a single logical connection through the PCIe bridge device. This consolidation maintains low latency by using direct PCIe-to-Pcie connections while reducing the apparent complexity by aggregating multiple physical links into one manageable interface for the host system.
Solution Approach 2:
The PCIe bridge device provides multi-functionality by handling both the physical link aggregation and the protocol translation functions. This universal device manages multiple links per connection internally while presenting a simplified interface externally, balancing low latency requirements with ease of configuration.
Data Source
AI summary
PCI Express (PCIE) is an IO interconnect standard that is implemented as a tree network with a root complex connecting to a CPU as the root node for use inside the computer for connecting to peripheral devices. Currently PCIE has achieved stability such that PCIE can be used as a basis for other applications. A PCIE based scheme inter-connecting multiple PCIE enabled computer systems each having at least one PCIE root complex controlling at least a PCIE bus, enabling the scalability of PCIE architecture to be applied for data transport between the connected system cluster is proposed. The interconnection uses an outbound port enabled for system interconnection on the PCIE bus of each PCIE enabled computer connecting to one inbound port on an independently programmable network switch having a plurality of inbound ports. The interconnection is using PCIE protocol for data transfer within the cluster.