PCIe Interface Controller With Flexible Port Configuration
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Solution Overview
Problem
Designing circuitry that can efficiently interface with the popular PCI Express (PCIe) standard while providing flexibility and cost-effectiveness is challenging due to the need for configuring interfaces and supporting multiple ports with varying lane configurations.
Innovation Solution
The implementation of a peripheral interface controller that includes serializer/deserializer (SERDES) circuits, receive and transmit pipes, multiplexing levels, accumulate buffers, and control logic to manage data flow and lane configurations, allowing for flexible configuration of ports over PCIe lanes, including lane reversal and various port sizes such as x1, x2, x4, x8, and x16.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple ports with varying lane configurations are supported, then adaptability is improved, but device complexity increases
Solution Approach 1:
The interface controller is divided into multiple SERDES quads, where each quad can be independently configured and activated. This segmentation allows the controller to support multiple port configurations by enabling or disabling specific quads, thereby achieving adaptability without requiring a completely different design for each configuration.
Solution Approach 2:
The controller implements dynamic configuration capabilities where ports can be programmed to use different numbers of lanes (x1, x2, x4, x8, x16) based on system requirements. The SERDES quads can be selectively activated or deactivated, allowing the interface controller to adapt its functionality and resource allocation in real-time, resolving the contradiction between versatility and complexity.
2Use of energy by moving object
If SERDES quads are selectively activated, then power consumption is reduced, but control complexity increases
Solution Approach 1:
The controller includes configuration registers that are programmed in advance to specify which SERDES quads should be activated and how ports should be configured. This preliminary configuration allows the system to power down unused quads while maintaining the desired port configurations, reducing power consumption without requiring complex real-time control decisions.
Solution Approach 2:
The control logic automatically manages the activation and configuration of SERDES quads based on the programmed settings in the configuration registers. Once configured, the system self-manages power distribution to active quads without requiring external intervention, simplifying the control complexity while achieving power reduction goals.
Data Source
AI summary
In one embodiment, an apparatus comprises serializer/deserializer (SERDES) circuits. Each SERDES circuit provides data received from a respective lane to which the SERDES circuit is coupled. A receive pipe is coupled to the SERDES circuits and comprises accumulate buffers, multiplexing levels, accumulate buffer counters, control registers, and control logic. Each accumulate buffer corresponds to a respective port configurable over the plurality of lanes. A first level of the multiplexing levels is coupled to receive data from neighboring lanes on one input and the data from the neighboring lanes connected in reverse order on the other input. Each multiplexor at each other level is coupled to receive outputs of neighboring multiplexors from a next lower level on one input and the outputs connected in reverse order on the other input. Each configuration register corresponds to a respective port, indicating an initial lane assigned to the respective port and a size of the port. The control logic is configured to generate select signals responsive to respective bits of the buffer counters and respective bits of initial lane numbers.