PCIe Interface Device Dynamic Traffic Class Allocation

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Solution Overview

Problem

Existing PCIe interface devices face challenges in providing uniform Quality of Service (QoS) across multiple functions due to varying throughputs, leading to potential bottlenecks and inefficient data transmission.

Innovation Solution

A PCIe interface device equipped with a performance analyzer to measure throughputs of multiple Direct Memory Access (DMA) devices and a traffic class controller to dynamically allocate traffic class values to transaction layer packets based on these measurements, ensuring optimal data routing and preventing bottlenecks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If multiple functions share the same PCIe interface without dynamic traffic class allocation, then device complexity is reduced, but Quality of Service uniformity deteriorates due to varying throughputs

Engineering Contradiction:
Improveinterface structureVSAvoidQoS uniformity
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent implements dynamic traffic class allocation where the PCIe interface device continuously monitors throughput of multiple functions and adjusts traffic class values in real-time. This dynamic adaptation ensures that functions with lower throughput receive higher priority traffic classes, maintaining uniform QoS across all functions while managing shared interface resources effectively

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent employs a feedback mechanism where the PCIe interface device measures the throughput of each function and uses this information to adjust traffic class allocations. The performance analyzer continuously monitors data transmission rates and feeds this information back to the traffic class allocator, which then optimizes packet prioritization to balance QoS across functions with varying throughput characteristics

Inventive Principle:
Principle #23Feedback

2Device complexity

If traffic class values are statically allocated to multiple functions, then device complexity is reduced, but productivity deteriorates due to bottlenecks in high-throughput functions

Engineering Contradiction:
Improvetraffic control mechanismVSAvoiddata transmission efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent transitions from static to dynamic traffic class allocation, where traffic class values are continuously adjusted based on real-time throughput measurements. This dynamic approach allows the system to adapt to changing data transmission demands, ensuring that high-throughput functions receive appropriate priority levels to maintain overall system productivity and prevent bottlenecks

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the traffic class parameter dynamically based on throughput conditions. Instead of fixed traffic class assignments, the system modifies traffic class values in response to measured throughput variations, allowing optimal data transmission efficiency across functions with different performance characteristics while maintaining manageable device complexity

Inventive Principle:
Principle #35Parameter changes

3Reliability

If throughput measurement and dynamic traffic class allocation are implemented, then QoS uniformity is improved, but device complexity increases

Engineering Contradiction:
ImproveQoS uniformityVSAvoidinterface control structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the PCIe interface device into distinct functional modules: a performance analyzer component that measures throughput, and a traffic class controller component that allocates traffic class values. This segmentation allows each component to perform its specific function independently, managing complexity through modular design while achieving uniform QoS through coordinated operation of the segments

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12007918B2Peripheral component interconnect express interface device and method of operating the same
Publication Date: 2024.06.11 SK HYNIX INC
  • US12007918B2 patent drawing
  • US12007918B2 patent drawing
  • US12007918B2 patent drawing

AI summary

Provided are a Peripheral Component Interconnect Express (PCIe) interface device and a method of operating the same. The PCIe interface device may include a performance analyzer and a traffic class controller. The performance analyzer may be configured to measure throughputs of multiple functions executed on one or more Direct Memory Access (DMA) devices. The traffic class controller may be configured to allocate traffic class values to transaction layer packets received from the multiple functions based on the throughputs of the multiple functions.