PCIe Bridge Interrupt Handling via Status Synchronization

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Solution Overview

Problem

In PCIe bridges, unpredictable data and status information transfer latency leads to interrupts bypassing corresponding status information, causing the host control module, interrupt module, and host memory to miss receiving status information when an interrupt is received.

Innovation Solution

A bridge system with buses, memory, and an interrupt module that detects network device interrupts and transmits an interrupt message via memory and buses to the host control module, ensuring that a second interrupt is generated only after status information is transmitted, indicating the completion of data transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If interrupts are transmitted directly from the network device to the PCIe interface without passing through the FIFO memory, then interrupt transmission speed is improved, but status information may be lost because interrupts can bypass corresponding status information

Engineering Contradiction:

Improveinterrupt transmission speedVSAvoidstatus information loss

Core Design Contradiction:

SpeedVSLoss of information

Solution Approach 1:

The patent introduces an interrupt module as an intermediary component between the PCIe interface and the host control module. This interrupt module receives interrupts from the PCIe interface, holds them temporarily, and releases them only after the corresponding status information has been successfully transmitted to the host memory. This mediator ensures that interrupts do not bypass their associated status information while maintaining efficient interrupt handling.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The system performs preliminary transmission of status information from the FIFO memory to the host memory before releasing the corresponding interrupt to the host control module. This preliminary action ensures that the host receives complete information (both status and interrupt) in the correct sequence, preventing information loss while maintaining speed efficiency.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If status information and data are transferred via FIFO memory with parallel data transfers, then data transfer throughput is improved, but transfer latency becomes unpredictable

Engineering Contradiction:

Improvedata transfer throughputVSAvoidunpredictable transfer latency

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent implements a feedback mechanism where the interrupt module monitors the transmission status of status information from the FIFO memory to the host memory. The interrupt release is conditioned on feedback confirming that status information has been successfully transmitted. This feedback loop provides predictable interrupt timing while maintaining high throughput through parallel FIFO operations.

Inventive Principle:

Principle #23Feedback

3Productivity

If multiple parallel data transfers are executed on internal buses with priority levels, then overall system productivity is improved, but interrupt timing precision deteriorates due to unpredictable latency

Engineering Contradiction:

Improveoverall system productivityVSAvoidinterrupt timing precision

Core Design Contradiction:

ProductivityVSMeasurement precision

Solution Approach 1:

The interrupt module serves as a mediator that decouples the interrupt generation from the data transfer completion. It receives interrupts independently of the parallel data transfer schedule, holds them until status information is confirmed transmitted, and then releases them. This intermediary approach maintains high system productivity through parallel transfers while achieving precise interrupt timing through controlled release.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS9128920B2Interrupt handling systems and methods for PCIE bridges with multiple buses

Publication Date: 2015.09.08 MARVELL ASIA PTE LTD

AI summary

A bridge includes buses, a memory, a component module, an interface and an interrupt module. The component module transfers data between a host control module and a network device via the memory and the buses. The interface is connected between the memory and the network device and transmits status information to the memory via one of the buses. The status information indicates completion of a last data transfer between the network device and the host control module. An interrupt module, subsequent to the status information being transmitted to the memory, detects a first interrupt generated by the network device, and transmits an interrupt message to the component module via the memory and the one of the buses. The component module then generates a second interrupt detectable by the host control module. The second interrupt indicates completion of data transfer between the network device and the host control module.