PCIe L1.2 Substate Wake-Up Time Configuration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The current PCI Express 4.0 Specification lacks flexibility in power and performance trade-off policies for devices in the L1.2 Substate, requiring three Configuration Write Requests and associated overhead for changing the L1.2 Exit time, limiting granular power-saving strategies.
Innovation Solution
Implementing Vendor Defined Messages (VDMs) and Vendor-Specific Extended Capability (VSEC) structures to dynamically configure L1.2 exit times during runtime, allowing hosts and PCIe devices to choose from multiple wake-up options, reducing latency and overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the PCIe 4.0 Specification uses a single L1.2-exit timing parameter (T_POWER_ON) to ensure no device actively drives into an unpowered component, then system reliability is improved, but power management flexibility and granularity are reduced
Solution Approach 1:
The patent segments the single T_POWER_ON parameter into multiple discrete timing options (e.g., T1, T2, T3 corresponding to different wake-up times). The host can selectively configure different wake-up times for different devices based on their specific power and performance requirements, while maintaining the reliability guarantee that no device actively drives into an unpowered component.
2Adaptability or versatility
If the host issues three Configuration Write Requests to change T_POWER_ON_SCALE and T_POWER_ON_VALUE, then the L1.2 exit time can be modified, but transaction overhead and latency increase
Solution Approach 1:
The patent merges the configuration of multiple wake-up time parameters into a single unified register structure (L1 PM Substates Control 2 Register). The host can configure multiple wake-up time options in one transaction, and the device can selectively apply different wake-up times based on current operational conditions, eliminating the need for multiple sequential Configuration Write Requests.
Solution Approach 2:
The host performs preliminary configuration by setting up multiple wake-up time options in advance within the device's register structure. This allows the device to quickly switch between different wake-up time configurations without requiring additional configuration transactions during runtime, reducing latency and overhead.
3Device complexity
If only one L1.2-exit timing parameter is architected in the PCIe Specification, then device complexity is reduced, but granular power-saving strategies are limited
Solution Approach 1:
The patent introduces dynamic configurability to the L1.2 exit timing mechanism. Instead of a fixed single parameter, the system now supports multiple configurable wake-up time options that can be dynamically selected based on real-time power and performance requirements. This allows fine-tuned power management strategies while maintaining a relatively simple register architecture.
Data Source
AI summary
Methods, apparatus, and systems for securely providing multiple wake-up time options for PCI Express (PCIe) devices. Under one approach, Vendor Define Messages (VDMs) are exchanged between a host application layer in a host and a device application layer in a PCIe endpoint device coupled to the host via a PCIe link to effect changes to the L1.2 Substate exit time of a PCIe device. Under another approach, Vendor-Specific Extended Capability (VSEC) structures are exchanged between a host application layer and a device application layer to effect the changes. The VDMs and VSEC structures may also be used to enable a host to read Tpower_on capability information defining power modes supported by a PCIe device. Additionally, VSEC implementations are provided that implement VSEC components in the PCIe device transaction layer or the PCIe device application layer.