PCIe Lane-Level Error Recovery in Flit Mode Links
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Solution Overview
Problem
The PCIe interface protocol experiences performance degradation due to the transmission of synchronization headers for each block, leading to all lanes transitioning to a recovery state even when only a single sync header mismatch occurs, resulting in significant performance loss.
Innovation Solution
An apparatus and method that transition from an L0 state to an L0p state for a portion of lanes with receiver errors, using equalization bypass, and transmit ordered sets through remaining lanes to maintain data communication without synchronizing timings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sync header is transmitted for each block to synchronize timings, then data transmission synchronization is improved, but transmission performance deteriorates due to overhead
Solution Approach 1:
The invention extracts the timing synchronization function from the traditional sync header mechanism and implements it through a different approach: using a loopback path that routes data from the transmit end back to the receive end without requiring explicit synchronization headers. This eliminates the overhead of sync headers while maintaining timing synchronization through the natural round-trip time measurement.
2Reliability
If all lanes transition to recovery state upon sync header mismatch, then error detection reliability is improved, but link availability deteriorates due to complete link interruption
Solution Approach 1:
The invention segments the error handling approach by lane, allowing individual lanes to be identified as having errors while other lanes continue normal operation. Instead of treating the link as a monolithic unit where any error causes complete failure, the system divides error management into lane-specific segments, enabling partial link functionality to be maintained.
Solution Approach 2:
The invention implements dynamic lane management where lanes can transition between active and recovery states independently based on their specific error conditions. This dynamic approach allows the link to adapt its configuration in real-time, maintaining optimal performance by keeping error-free lanes active while isolating problematic lanes for recovery.
3Speed
If equalization bypass is used to reach specific data rate, then link initialization speed is improved, but error recovery flexibility deteriorates
Solution Approach 1:
The invention performs preliminary equalization measurements during link initialization using the loopback path before actual data transmission begins. By pre-characterizing the channel properties and establishing baseline performance metrics, the system prepares for potential error conditions without delaying link activation. This preliminary action enables faster initialization while maintaining the capability to adapt to errors that arise during operation.
Data Source
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AI summary
An apparatus includes a port that is connected to a link including plural lanes to support communication between the apparatus and another device and that transmits a flit in a flit mode, and a processor that controls the link based on a link training and status state machine (LTSSM). The processor transitions from an L0 state to an L0p state, included in the LTSSM, for a portion of the plural lanes based on a receiver error occurring in the portion of the plural lanes and based on the link reaching a specific data rate using equalization bypass, and the port, after transitioning to the L0p state, transmits an ordered set (OS) through the portion of the plural lanes and transmits the flit through remaining lanes of the plural lanes.