PCIe Link Aggregation for Bandwidth Bottlenecks

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Solution Overview

Problem

Portable computing devices with integrated and discrete graphics processing units face performance issues due to inefficient PCI-e interface configurations, where unoccupied links result in substandard performance and wasted bandwidth, especially when used with network controllers.

Innovation Solution

A link aggregator system that combines unoccupied PCI-e interface links with occupied links to increase bandwidth for discrete graphics processing units, distributing memory access requests evenly among aggregated links to enhance data transfer rates and processing performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If PCI-e interface is configured with multiple separate links for different peripheral devices, then device connectivity and versatility are improved, but bandwidth availability for each individual device is reduced

Engineering Contradiction:
Improvedevice connectivityVSAvoidbandwidth availability
Core Design Contradiction:
Adaptability or versatilityVSPower

Solution Approach 1:

The system dynamically allocates PCI-e links based on device needs. When a device requires high bandwidth, the system aggregates available links to create a dynamic high-bandwidth connection. When bandwidth is not needed, links remain available for other devices or are put in low-power states, optimizing the trade-off between connectivity and bandwidth availability.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The PCI-e interface is segmented into multiple independent links that can be independently configured and allocated. This segmentation allows the system to divide bandwidth resources among multiple devices while maintaining the ability to aggregate links when needed, resolving the contradiction between providing multiple connections and maintaining high bandwidth for each.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If unoccupied PCI-e links are left unused, then device complexity is reduced, but bandwidth waste increases

Engineering Contradiction:
Improvelink configurationVSAvoidbandwidth waste
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The system automatically detects when additional bandwidth is needed and autonomously aggregates available unoccupied links to support high-bandwidth devices. This self-service mechanism eliminates the need for manual link configuration while preventing bandwidth waste by ensuring all available links are productively utilized when demand arises.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system changes the operational state of unoccupied links from idle to active by aggregating them with occupied links. This parameter change transforms unused bandwidth capacity into useful resource, increasing overall system efficiency without requiring changes to the physical hardware configuration or increasing device complexity.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If discrete graphics processing units are added to portable devices, then processing capability is improved, but power consumption increases

Engineering Contradiction:
Improveprocessing capabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system dynamically allocates PCI-e links to graphics processing units based on performance demands. When high processing capability is needed, additional links are aggregated to provide high bandwidth to the discrete GPU. When processing demands are lower, the system can reduce link allocation or switch to integrated graphics, optimizing the trade-off between processing capability and power consumption.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9176909B2Aggregating unoccupied PCI-e links to provide greater bandwidth
Publication Date: 2015.11.03 NVIDIA CORP
  • US9176909B2 patent drawing
  • US9176909B2 patent drawing
  • US9176909B2 patent drawing

AI summary

Embodiments of the claimed subject matter are directed to systems and a method that allows the aggregation of multiple interfaces of a single data communication bus to provide greater bandwidth for communication between a peripheral device and system memory within a computing system. In one embodiment, a system is provided wherein the unoccupied interfaces of the data communication bus is aggregated with an occupied interface coupled to a peripheral device to increase the bandwidth of data transfer requests between the peripheral device and the system memory.