Adaptive PCIe Link Speed and Width Control for BER Recovery
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Solution Overview
Problem
Existing PCIe links experience performance degradation due to various errors and exceptional situations, leading to interrupted communication and reduced data transfer rates, despite following the PCIe standard.
Innovation Solution
A semiconductor device and method that dynamically adjust link speed and width based on bit error rates and transition counts, using a controller to manage PCIe links and implement LTSSM rules to maintain communication continuity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the PCIe link operates at high speed with high link width, then data transfer rate is improved, but communication continuity and reliability deteriorate due to errors and performance degradation
Solution Approach 1:
The patent applies preliminary action by proactively detecting link status through DLLP packets and transitioning to recovery state before severe errors occur. The controller monitors bit error rates and link width changes, taking preventive measures to maintain communication continuity rather than reacting after failures happen.
Solution Approach 2:
The patent implements dynamics by dynamically adjusting link width and speed based on real-time error conditions. The link configuration changes from fixed to adaptive, allowing the system to optimize between speed and reliability based on current operational status and detected errors.
2Reliability
If the PCIe link speed is reduced to improve reliability, then communication continuity is improved, but data transfer rate deteriorates
Solution Approach 1:
The patent applies dynamics by making link speed adaptive rather than fixed. The system dynamically adjusts speed based on error conditions, transitioning between high-speed operation and reduced-speed recovery modes to optimize both reliability and productivity according to actual link health.
Solution Approach 2:
The patent implements parameter changes by modifying link speed and width parameters based on detected errors. The controller changes operational parameters (speed, width) to balance between maintaining high data transfer rates and ensuring communication reliability based on real-time monitoring.
3Reliability
If the link width is reduced to maintain communication continuity, then reliability is improved, but productivity deteriorates
Solution Approach 1:
The patent applies dynamics by making link width adaptive based on error conditions. The system dynamically adjusts the number of active lanes, transitioning from full width operation to reduced width recovery modes to maintain communication continuity while optimizing productivity based on actual link status.
Solution Approach 2:
The patent implements parameter changes by modifying link width as a dynamic parameter. The controller changes the operational width based on detected errors and link health, allowing the system to balance between maintaining high productivity and ensuring reliability through real-time parameter adjustment.
4Reliability
If the PCIe link frequently transitions between L0 and L0p states, then error recovery is improved, but communication continuity deteriorates due to repeated transitions
Solution Approach 1:
The patent applies preliminary action by proactively managing transitions and preventing excessive L0-L0p cycling. The controller monitors transition counts and takes preventive actions to stabilize the link state, reducing unnecessary transitions that would cause communication interruptions.
Solution Approach 2:
The patent implements feedback by monitoring transition counts and using this information to control future transitions. The system uses feedback from transition monitoring to determine when to stabilize in L0p state versus when to return to L0, optimizing both error recovery and communication continuity.
Data Source
AI summary
Provided are a semiconductor device for changing a link speed and a link width of a peripheral component interconnect express (PCIe) link and an operating method thereof. The semiconductor device includes the PCIe link including a plurality of lanes, and a controller configured to transceive a data link layer packet (DLLP) including a number of times of transition and a maximum number of times of transition from an L0 state to an L0p state through the PCIe link, based on a first bit error rate (BER) of a data packet received through the PCIe link and a first criterion value in the L0 state, and determine whether to perform at least one of a link speed changing operation performed in a recovery state, or a link width changing operation performed in the L0p state, based on the number of times of transition and the maximum number of times of transition.