PCIe Link Controller Fail Lane Segmentation
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Solution Overview
Problem
PCIe devices face challenges in establishing a stable link when a fail lane is detected during the link setting operation, as existing technologies do not effectively manage the failure of individual lanes, leading to reduced performance and efficiency in data transmission.
Innovation Solution
A PCIe device and computing system that detect a fail lane during the link setting process and configure the remaining lanes to form a link, ensuring that the link width includes only the operational lanes, thereby excluding the fail lane and maintaining data transmission through logically continuous lanes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all lanes are used to form a link, then the link width and data transmission capacity are maximized, but the system reliability deteriorates when a fail lane is detected
Solution Approach 1:
The link is segmented into multiple lanes, and the fail lane detection mechanism divides the lanes into operational and non-operational groups. When a fail lane is detected, the link controller segments the link width to exclude only the failed lane while maintaining connectivity through remaining lanes, thus preserving overall link functionality despite partial failure.
Solution Approach 2:
The link width parameter is dynamically adjusted based on lane operational status. When a fail lane is detected during link setting, the link width is changed from the original full width to a reduced width that excludes only the failed lane, allowing the link to adapt to the actual operational capacity and maintain stable data transmission.
2Reliability
If the link setting process is strict about lane failure, then the link stability is ensured, but the productivity decreases due to reduced link width
Solution Approach 1:
The fail lane is extracted and removed from the active link configuration. When a fail lane is detected, the link controller identifies and extracts the failed lane from the link width, allowing the remaining operational lanes to form a stable link without the harmful influence of the failed lane, thus maintaining both stability and optimal performance.
Solution Approach 2:
The presence of a fail lane, which initially appears as a harmful factor, is converted into a benefit through the fail lane detection and exclusion mechanism. By detecting and excluding the fail lane, the system transforms a potential source of instability into an opportunity to optimize the link width to match actual operational capacity, improving overall link reliability and performance.
3Reliability
If the link width is reduced to exclude fail lanes, then the link reliability is improved, but the device complexity increases due to fail lane detection and management
Solution Approach 1:
The link controller performs self-service by automatically detecting fail lanes during the link setting process and autonomously adjusting the link width to exclude failed lanes. This self-service capability eliminates the need for external intervention or complex manual configuration, managing the complexity internally while maintaining simple operation for the user and improving link reliability.
Data Source
AI summary
A PCIe device setting, when a fail lane is detected during a link setting operation, a link by using remaining lanes includes a plurality of lanes comprising a plurality of ports, and a link controller setting a link including the plurality of lanes, wherein the link is set to have a link width that includes remaining lanes, except for a fail lane from among the plurality of lanes, wherein the fail lane from among the plurality of lanes has a state in which the fail lane is unable to form a link with remaining lanes that have not failed from among the plurality of lanes.