PCIe Link Retraining via CPLD Register Control for Bandwidth Slowdown
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Solution Overview
Problem
Peripheral Component Interconnect Express (PCIE) devices experience bandwidth slowdown during startup or restart, requiring a lengthy reset process that takes 16 seconds, which is inefficient and affects device startup time.
Innovation Solution
A method and apparatus that utilize a BIOS module connected to a CPLD module with a register to acquire and compare link bandwidth of a PCIE module, sending register connection state control instructions to the CPLD to enable and disable connections, thereby initializing and retraining the link to repair bandwidth slowdowns in milliseconds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the PCIE device is reset twice by the CPU to repair bandwidth slowdown, then the bandwidth slowdown can be repaired, but the device startup time increases significantly (16 seconds required for stabilization between resets)
Solution Approach 1:
The patent introduces a CPLD (Complex Programmable Logic Device) as an intermediary component between the CPU and PCIE device. The CPLD receives control instructions from the BIOS module and directly manages the PCIE device's register connections, enabling bandwidth repair without requiring repeated CPU resets. This intermediary approach eliminates the 16-second stabilization wait time while maintaining effective bandwidth repair.
Solution Approach 2:
The patent replaces the mechanical reset process (CPU-based hardware reset requiring stabilization time) with a software-controlled register operation (BIOS module sending control instructions to CPLD). By substituting the physical reset mechanism with a logical register control mechanism, the system achieves bandwidth repair without the time-consuming hardware reset cycle.
2Reliability
If the CPU performs repeated resetting operations on the PCIE device, then the bandwidth slowdown is repaired, but the processing efficiency and timeliness of repair deteriorate
Solution Approach 1:
The CPLD acts as an intermediary that enables direct register control of the PCIE device by the BIOS module, bypassing the need for repeated CPU reset operations. This intermediary mechanism achieves bandwidth repair through efficient register manipulation rather than time-consuming reset cycles, significantly improving repair timeliness.
Solution Approach 2:
The patent changes the operational parameter from repeated reset operations to single control instruction execution. By modifying the repair mechanism from time-intensive resets to parameter-based register control, the system achieves the same bandwidth repair effect with dramatically improved timeliness and productivity.
Data Source
AI summary
The present application provides a method and apparatus for repairing bandwidth slowdown, an electronic device, and a storage medium, applied to a BIOS module. The BIOS module is connected to a CPLD module with a register and is configured to communicate with the CPLD module; and the CPLD module is connected to a PCIE module configured with a target bandwidth and is configured to acquire a link bandwidth of the PCIE module. The method includes: acquiring the link bandwidth of the PCIE module from the CPLD module when a device is started; comparing the link bandwidth with the target bandwidth, and determining whether the PCIE module has the bandwidth slowdown; and sending a register connection state control instruction to the CPLD module when the PCIE module has the bandwidth slowdown, so that the register performs enable and disable connection operations in response according to the received instruction.