PCIe Link Equalization Using Fail Lane Detection and EQ Coefficients
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Solution Overview
Problem
PCIe devices face challenges in establishing reliable links due to fail lanes, which can disrupt data communication and require inefficient reconfiguration of remaining lanes, leading to performance degradation.
Innovation Solution
A PCIe device and method that detect fail lanes during link setting, utilize remaining lanes to establish a link, and perform improved equalization operations using EQ controllers to determine optimal EQ coefficients based on log information and error data, ensuring efficient transmitter and receiver settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a PCIe link includes all lanes, then the link width is maximized, but a fail lane can disrupt data communication and require inefficient reconfiguration
Solution Approach 1:
The patent segments the PCIe link into individual lanes, allowing the system to identify and exclude fail lanes while maintaining operational lanes. The link controller divides the link configuration process into lane-by-lane detection and configuration, enabling selective activation of healthy lanes only, thus improving reliability without requiring complete reconfiguration of all lanes.
Solution Approach 2:
The patent changes the link width parameter dynamically based on lane health status. Instead of fixed link configuration, the system adjusts the number of active lanes from the full width to a reduced width excluding fail lanes. This parameter adaptation allows the link to maintain optimal performance with available healthy lanes while avoiding the complexity of reconfiguring entire link settings.
2Reliability
If traditional equalization operation is performed, then transmitter and receiver settings are determined, but the process is time-consuming and may fail repeatedly
Solution Approach 1:
The patent performs preliminary actions by storing EQ coefficient information in non-volatile memory before link operation. The EQ controller retrieves pre-stored EQ coefficients for different link widths and lane configurations, eliminating the need to perform time-consuming equalization operations from scratch each time a link is established or reconfigured.
Solution Approach 2:
The patent implements feedback mechanisms where the EQ controller monitors equalization results and uses this information to select optimal EQ coefficients for future operations. The system stores feedback data about successful EQ configurations and uses this historical information to accelerate subsequent equalization processes, reducing time loss while maintaining reliability.
3Adaptability or versatility
If link reconfiguration is performed after fail lane detection, then remaining lanes can be utilized, but the reconfiguration process is inefficient
Solution Approach 1:
The patent implements self-service by enabling the link controller to automatically detect fail lanes and reconfigure the link without external intervention. The system autonomously identifies healthy lanes, selects appropriate EQ coefficients, and establishes operational links independently, improving adaptability while reducing the time and complexity associated with manual or inefficient reconfiguration processes.
Data Source
AI summary
A Peripheral Component Interconnect Express (PCIe) device includes a plurality of lanes comprising a plurality of ports, a link controller setting a link including the plurality of lanes, wherein the link is set to have a link width that includes the remaining of lanes, except for a fail lane from among the plurality of lanes, and an EQ controller performing an equalization operation for determining a transmitter or receiver setting of each of the remaining lanes, wherein the EQ controller determining a final EQ coefficient using a log information and an error information.