PCIe Link Equalization Using Preliminary Phase 2 Settings
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Solution Overview
Problem
Existing electronic devices connected via PCIe interfaces face challenges in maintaining signal quality, particularly when certain phases of the link equalization sequence are omitted, as they need to ensure bit error rates (BER) below 10−12 across different communication speeds, such as Gen3 and Gen4, without executing all phases of the link equalization sequence.
Innovation Solution
The electronic device determines the initial value of TxEQ for the host in Gen4 based on the results from Phase 2 of the link equalization sequence in Gen3, using the optimal TxEQ and RxEQ code values to adjust the equalizer settings, ensuring the reception characteristics meet the required BER, even if Phase 2 or Phase 3 of the Gen4 sequence is omitted.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the link equalization sequence phases are omitted to reduce communication time, then productivity is improved, but signal quality deteriorates making it difficult to maintain BER < 10^-12
Solution Approach 1:
The patent applies preliminary action by performing link equalization at Gen3 speeds before transitioning to Gen4 communication. Phase 2 and Phase 3 of the link equalization sequence are executed at the lower Gen3 speed to establish optimal equalizer settings, which are then reused during Gen4 operation. This preliminary equalization ensures signal quality requirements are met when higher-speed communication begins, resolving the contradiction between maintaining signal quality and achieving high productivity.
2Reliability
If all phases of the link equalization sequence are executed to ensure signal quality, then reliability is improved, but communication time increases reducing productivity
Solution Approach 1:
The patent segments the link equalization process into distinct phases executed at different speeds. Phase 1 is executed at Gen4 speed for initial connection, while Phase 2 and Phase 3 are executed at the slower Gen3 speed to perform detailed equalization without impacting overall communication time. This segmentation allows critical equalization tasks to be performed thoroughly while maintaining high productivity during data transmission phases.
Solution Approach 2:
The patent performs the time-consuming Phase 2 and Phase 3 equalization operations as preliminary actions at Gen3 speeds before initiating high-speed Gen4 communication. By completing these equalization phases in advance at lower speeds, the system ensures signal quality requirements are satisfied without delaying the start of productive high-speed data transmission.
3Device complexity
If the host transmission equalizer setting is fixed to simplify configuration, then device complexity is reduced, but adaptability deteriorates making it difficult to maintain BER across different communication speeds
Solution Approach 1:
The patent implements dynamic adaptation by automatically adjusting the host transmission equalizer setting based on the detected PCIe generation. When Gen4 operation is detected, the system dynamically modifies the host TxEQ initial value using information from Gen3 equalization results. This dynamic adjustment mechanism maintains compatibility across different PCIe generations without requiring complex manual configuration, resolving the contradiction between simplicity and adaptability.
Solution Approach 2:
The patent changes the TxEQ parameter values based on communication speed and PCIe generation. By modifying the initial TxEQ setting for the host according to whether Gen3 or Gen4 operation is being performed, the system adapts to different communication requirements while maintaining a relatively simple overall configuration process. The parameter changes are automatically applied based on detected conditions rather than manual intervention.
Data Source
AI summary
According to one embodiment, in a first state, a control circuit determines, based on first information and second information, information on a request that includes a setting of a transmission circuit of a host to be set as an initial setting in a second state. The first state is a state of communicating with a host at a first communication speed conforming to a first specification. The second state is a state of communicating with the host at a second communication speed conforming to a second specification. The second communication speed is different from the first communication speed. The first information is information on a request of a setting of the transmission circuit of the host. The second information is information on a quality of a signal received by a reception circuit, which has been transmitted from the transmission circuit of the host.