PCIe Link Power Management Control for System Stability

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Solution Overview

Problem

The existing power management systems for PCI Express links between chipsets and devices face instability and system hangs when transitioning between operating states, particularly when entering standby modes, due to the enabling of L0s and L1 ASPM states, which can lead to unintended power management states like L2 or L3, causing system instability and errors.

Innovation Solution

A power management apparatus and method that disables L0s and L1 states when the system enters S3 or S4 states and reactivates them upon resumption, using a BIOS-directed driver to manage ASPM states and transition power to lower states based on idle conditions and traffic generation, ensuring stable system recovery and efficient power usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If L0s and L1 ASPM states are enabled to save power, then power consumption is reduced, but system stability deteriorates causing hangs and blue screens during standby mode transitions

Engineering Contradiction:
Improvepower consumptionVSAvoidsystem stability
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The patent applies dynamics by making the ASPM state configuration changeable based on system operating conditions. The driver dynamically enables or disables L0s/L1 states depending on whether the system is in suspend mode or normal operation, allowing the power management behavior to adapt to different operational contexts rather than being fixed

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of ASPM state availability based on system state. When the system enters suspend mode (S3/S4), the driver modifies the power management parameters to disable L0s/L1 states, preventing instability. When resuming, the parameters are restored to enable power-saving states again

Inventive Principle:
Principle #35Parameter changes

2Reliability

If ASPM functions are disabled to ensure stability, then system reliability is maintained, but power saving capability is lost

Engineering Contradiction:
Improvesystem stabilityVSAvoidpower saving capability
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The driver implements dynamic control of ASPM functionality, transitioning between enabled and disabled states based on system operational mode. This allows the system to achieve both stability during suspend and power savings during normal operation through conditional enabling/disabling

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The driver performs preliminary configuration changes when entering suspend mode by disabling ASPM states before the actual power-saving transition occurs. This preventive action ensures stability during the critical transition period while maintaining the ability to enable power-saving states when safe

Inventive Principle:
Principle #10Preliminary action

3Loss of energy

If Link power management states are allowed to transition freely, then power efficiency is improved, but unintended power states cause system instability

Engineering Contradiction:
Improvepower efficiencyVSAvoidsystem instability
Core Design Contradiction:
Loss of energyVSObject-affected harmful factors

Solution Approach 1:

The driver implements feedback control by monitoring system state transitions and using this information to adjust ASPM configuration. When detecting suspend mode entry, the driver responds by disabling L0s/L1 states, creating a closed-loop control system that prevents harmful state transitions based on real-time system conditions

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8090968B2Apparatus and method for power management control
Publication Date: 2012.01.03 LG ELECTRONICS INC
  • US8090968B2 patent drawing
  • US8090968B2 patent drawing
  • US8090968B2 patent drawing

AI summary

A power management control apparatus including a memory unit configured to store a program for disabling a previously determined Link power management state when a system enters a specific operating state and for enabling the disabled Link power management state when the system is resumed, a processor configured to access the memory unit and to execute the program, and a control unit connected to the processor and the memory unit and configured to manage Link power based on a result of executing the program.