PCI Express Link Speed Auto-Negotiation for Bridge Compatibility
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Solution Overview
Problem
Incompatibility of link speeds between PCI Express bridges and peripheral devices due to different versions can lead to failed connections, causing systems to fail to recognize and utilize add-on cards, resulting in instability and requiring manual reboot and speed adjustments.
Innovation Solution
A method that automatically adjusts the link speed between a bridge and a peripheral device by reading bus information, selecting a target bridge, determining the maximum supported speed, testing access, and iteratively adjusting the speed until a valid connection is established, ensuring compatibility and proper device recognition during the bus enumeration procedure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the link speed is set to the maximum supported speed, then the communication efficiency is improved, but the compatibility with different PCI Express versions deteriorates
Solution Approach 1:
The patent implements dynamic link speed adjustment by automatically detecting the PCI Express version and negotiating the appropriate link speed between the bridge and peripheral device. The system transitions from static speed configuration to dynamic speed negotiation, selecting the optimal speed (e.g., 2.5 GT/s, 5.0 GT/s, or 8.0 GT/s) based on the detected device capabilities and version compatibility.
Solution Approach 2:
The patent changes the link speed parameter based on the detected PCI Express version and device compatibility. The system adjusts the link speed parameter dynamically during the bus enumeration procedure, transforming it from a fixed hardware setting to a negotiable software-controlled parameter that adapts to different device versions.
2Adaptability or versatility
If the link speed is manually adjusted down via BIOS options, then the compatibility is improved, but the ease of operation deteriorates
Solution Approach 1:
The patent implements self-service by enabling the system to automatically detect PCI Express device versions and negotiate appropriate link speeds without requiring user intervention. The BIOS automatically performs version detection, compatibility checking, and link speed negotiation, eliminating the need for users to manually adjust BIOS settings when encountering compatibility issues.
Solution Approach 2:
The patent introduces feedback mechanisms where the system detects the response of peripheral devices during the bus enumeration procedure and automatically adjusts link speeds based on this feedback. If a device is not recognized or compatibility issues arise, the system receives feedback about the failure and automatically negotiates a lower link speed to establish successful communication.
3Adaptability or versatility
If the link speed is forcedly adjusted to the slowest speed, then the compatibility is improved, but the productivity deteriorates
Solution Approach 1:
The patent implements dynamic link speed selection that transitions from static forced slow-speed operation to dynamic speed negotiation. The system automatically detects device capabilities and selects the optimal link speed from multiple options (2.5 GT/s, 5.0 GT/s, 8.0 GT/s), ensuring both compatibility and maximum communication efficiency rather than forcing the slowest speed universally.
4Reliability
If the system requires manual reboot and speed adjustments, then the reliability is improved through user control, but the loss of time increases
Solution Approach 1:
The patent performs preliminary action by conducting automatic link speed negotiation and compatibility detection during the early boot process before the operating system loads. The system proactively detects PCI Express device versions, negotiates appropriate link speeds, and establishes stable connections during the bus enumeration procedure, preventing compatibility issues before they affect system operation and eliminating the need for subsequent reboots.
Data Source
AI summary
A method for adjusting a link speed and a computer system using the same are provided. The method is used after executing a boot block code and before executing a bus enumeration procedure. A testing step is executed using a maximum link speed supported by both a bridge and a peripheral device. If the test fails, the link speed is adjusted down until the test succeeds, thus automatically adjusting the link speed of the bridge.