PCIe Link Speed Switching Latency Reduction
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Solution Overview
Problem
Current PCIe link speed switching methods interrupt data communication by disabling the link during training, recovery, and configuration, leading to potential data loss and latency issues.
Innovation Solution
The solution involves training and configuring idle lanes to a new speed while active lanes continue to operate, allowing seamless data transfer by switching data traffic to the newly configured lanes once they are ready, thus minimizing latency and maintaining continuous communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the link is disabled during training, recovery, and configuration when switching PCIe link speeds, then the link can be properly reconfigured to the new speed, but data communication is interrupted causing latency and potential data loss
Solution Approach 1:
The PCIe link is divided into multiple independent lanes. During a speed transition, only a subset of lanes (first subset) is taken offline for training and reconfiguration, while other lanes (second subset) remain active and continue data transmission. This segmentation allows the link to be partially updated without complete interruption.
Solution Approach 2:
The controller initiates the speed transition by selecting which lanes will transition and preparing them in advance. The first subset of lanes is identified and prepared for reconfiguration before the actual speed change occurs, allowing a smooth handover from active to inactive state while maintaining overall link continuity.
2Reliability
If all lanes are taken offline for training during speed switching, then complete reconfiguration to the new speed is achieved, but data transfer is completely stopped causing service interruption
Solution Approach 1:
The set of lanes is segmented into at least two subsets: a first subset that undergoes training and reconfiguration, and a second subset that remains active. This ensures that while some lanes are being reconfigured for reliability, others maintain data transfer productivity without interruption.
Solution Approach 2:
The second subset of lanes continues to carry data traffic throughout the reconfiguration process of the first subset. This maintains continuous useful action (data transfer) while allowing necessary maintenance and reconfiguration activities to proceed on the first subset, ensuring both reliability and productivity are preserved.
Data Source
AI summary
Aspects relate to link speed for a peripheral component interconnect. In one aspect, an apparatus includes an interface circuit configured to provide an interface with a multiple lane data link, the data link having a first set of lanes in an active state and a second set of lanes in an idle state and a controller. The controller is configured to receive a request at the controller to change a data rate of the data link to a requested data rate, change the second set of lanes from an idle state to an active state, train the second set of lanes to the requested data rate, transfer data traffic from the first set of lanes to the second set of lanes after the training, and transmit the data traffic on the second set of lanes.