PCIe Link Speed Throttling for Discrete USB4 Host Power Savings
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Solution Overview
Problem
Existing USB4 and Thunderbolt technologies face challenges in optimizing power consumption due to increased bandwidth, leading to higher power consumption by the physical layer (PHY) and controller, which affects battery life and thermal performance, especially in discrete host configurations where existing power management policies are limited to downstream link states without dynamic speed adjustments.
Innovation Solution
Implement a mechanism to dynamically adjust the PCIe host controller link speed based on system-level policies and application needs, using a software connection manager to throttle the link speed according to bandwidth consumption and peripheral connections, thereby reducing power consumption and optimizing power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If USB4/Thunderbolt technologies use increased bandwidth for high-speed data transmission, then data transfer performance is improved, but power consumption by the physical layer and controller increases
Solution Approach 1:
The patent implements dynamic link speed adjustment by transitioning the PCIe host controller link between different generation speeds (Gen3, Gen4, Gen5) based on system-level policies and application needs. The software connection manager monitors bandwidth consumption and peripheral connections, then throttles or increases link speed accordingly, making the power consumption adaptable to actual usage patterns rather than fixed at maximum bandwidth.
Solution Approach 2:
The patent changes the operational parameters of the PCIe link by adjusting the link speed generation (Gen3: 8GT/s, Gen4: 16GT/s, Gen5: 32GT/s) based on system conditions. This parameter adjustment allows the system to operate at lower power consumption levels (Gen3) when full bandwidth is not needed, while still providing high-speed capability (Gen5) when applications require maximum performance, thus resolving the contradiction between speed and power usage.
2Productivity
If the PCIe host controller operates at maximum bandwidth, then data transmission performance is improved, but battery life is reduced
Solution Approach 1:
The system dynamically adjusts the PCIe link operating speed based on real-time monitoring of bandwidth consumption and peripheral connections. When applications are idle or using minimal bandwidth, the link throttles to lower generations (Gen3), conserving battery power. When applications require high data transmission performance, the link scales up to Gen4 or Gen5, ensuring productivity is maintained only when actually needed, thus extending overall battery life.
Solution Approach 2:
The software connection manager implements a feedback mechanism that continuously monitors system-level policies, application bandwidth needs, and peripheral connection states. Based on this feedback, the system adjusts the PCIe link speed accordingly, creating a closed-loop control system that optimizes the balance between productivity and battery life by matching power consumption to actual data transmission requirements.
3Device complexity
If existing power management policies are limited to downstream link states only, then implementation complexity is reduced, but power optimization capability is insufficient
Solution Approach 1:
The patent extends power management from static downstream link states to dynamic upstream link speed adjustments. By implementing software-based throttling of the PCIe host controller link speed (Gen3/Gen4/Gen5 transitions) in addition to traditional downstream state management, the system achieves comprehensive power optimization without excessive complexity, as the throttling mechanism leverages existing PCIe configuration interfaces and system-level policy frameworks.
Data Source
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AI summary
Embodiments herein relate to reducing the power consumption of a serial link (103) such as Peripheral Component Interconnect Express (PCIe) link (103). The link (103) may extend between a System-On-A-Chip, SoC, (101) and a Universal Serial Bus, USB4, host (102) in a computing device (100). The USB4 host includes a PCIe switch (150) which connects lanes of the link (103) to adapters (171 - 177) in a USB4 router (170), such as a USB3 adapter (171, 172), a PCIe adapter (173, 174), a host interface adapter (175) and a DisplayPort adapter (176, 177). The available bandwidth of the link (103) can be adjusted based on a measured data rate. For example, the data rate can be compared to one or more thresholds. In one approach, the data rate is based on downstream transmissions, from the SoC (101) to the USB4 host (102). A transmitter clock rate can be adjusted to adjust the bandwidth and reduce power consumption.