PCIe Link-Status Logging for Completion Timeout Identification

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Solution Overview

Problem

Current technologies lack the ability to identify the cause of completion timeouts in PCIe networks, as completion timeout information is not stored in header log registers, making it difficult to determine whether the issue is with the requester, completer, or the link between them.

Innovation Solution

An information processing apparatus that stores link-status information to identify errors, including a method to obtain and analyze link-status information when a response is not received within a predetermined time, allowing for the identification of the link or device causing the completion timeout.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If completion timeout detection is implemented in the requester, then the ability to detect errors is improved, but the ability to identify the cause of the error deteriorates because no log is stored

Engineering Contradiction:
Improveerror detection capabilityVSAvoidcause identification difficulty
Core Design Contradiction:
ReliabilityVSDifficulty of detecting and measuring

Solution Approach 1:

The patent introduces an intermediary logging mechanism that captures completion timeout information from the requester and stores it in a format that can be analyzed. This intermediary layer bridges the gap between error detection and cause identification by systematically recording timeout events and their contextual information.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements preliminary logging of completion timeout information before the error analysis phase. By pre-capturing and storing timeout data in structured logs, the system prepares the information needed for subsequent cause identification, eliminating the need for complex real-time analysis when an error occurs.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If link-status information is stored in multiple devices, then the precision of error location identification is improved, but the complexity of the system increases

Engineering Contradiction:
Improveerror location identification precisionVSAvoidsystem complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the error identification task by distributing link-status information storage across multiple devices along the PCIe path. Each device maintains its own status information, allowing the system to pinpoint errors to specific segments or hops in the communication path without requiring a complete system-wide monitoring infrastructure.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9665456B2Apparatus and method for identifying a cause of an error occurring in a network connecting devices within an information processing apparatus
Publication Date: 2017.05.30 FSAS TECH INC
  • US9665456B2 patent drawing
  • US9665456B2 patent drawing
  • US9665456B2 patent drawing

AI summary

An information processing apparatus includes a plurality of devices, each including a memory that stores link-status information indicating whether or not an error occurs in a link connected to the each device. When a first device among the plurality of devices fails to receive within a predetermined time period a response for a request that has been transmitted by the first device, the first device obtains the link-status information from relevant devices each related to at least one of transfer of the request and transfer of the response, and identifies a link in which the error has occurred or a device that is connected to the link, based on the obtained link-status information.