PCIe Link Training Adaptation for Interoperability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing computer bus protocols like PCIe face high software overhead due to the need for backward compatibility with older versions, requiring repetitive link training sequences and increased complexity during initialization.
Innovation Solution
A method and device that dynamically adjust the link training sequence symbols based on the number of failures, switching from higher version (e.g., PCIe 2.0 or 3.0) to lower version (e.g., PCIe 1.x) settings when a predetermined threshold of failures is reached, allowing interoperability between devices compliant with different PCIe versions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If PCIe 2.0 or 3.0 devices initially advertise themselves as PCIe 1.1 devices for backward compatibility, then compatibility with PCIe 1.x devices is maintained, but software overhead increases due to repetitive link training sequences
Solution Approach 1:
The device performs preliminary detection of receiver presence on each lane before initiating link training. By detecting whether a receiver is present and counting link training failures in advance, the system can determine the appropriate PCIe version to use, avoiding repetitive training sequences and reducing software overhead while maintaining compatibility
Solution Approach 2:
The system implements a feedback mechanism by counting link training failures and using this information to dynamically adjust the advertised PCIe version. When failures reach a threshold, the device switches from advertising PCIe 2.0/3.0 to PCIe 1.1, creating a self-regulating system that optimizes both compatibility and performance
2Reliability
If link training sequences are repeated to ensure compatibility, then interoperability between different PCIe versions is achieved, but initialization complexity increases
Solution Approach 1:
The system dynamically adjusts the link training process based on real-time feedback. Instead of using a static initialization process, the device monitors link training failures and adapts its behavior by switching between PCIe 2.0/3.0 and PCIe 1.1 modes, simplifying the initialization process while ensuring reliable interoperability
3Speed
If PCIe 2.0 or 3.0 signaling mode is used, then data transfer rate increases to 500 MBIs or 1 GBIs, but compatibility with PCIe 1.x devices decreases
Solution Approach 1:
The system changes the signaling parameter dynamically based on the detected receiver capability and link training success. The device can operate at PCIe 2.0/3.0 speeds (500 MBIs/1 GBIs) when compatible devices are detected, and automatically switch to PCIe 1.1 signaling when incompatibility is detected, optimizing both speed and compatibility
Data Source
AI summary
A method and a device for disabling a lower version of a computer bus and interconnection protocol (e.g., Peripheral Component Interconnect Express (PCIe) 2.0 or higher) for interoperability with a receiver compliant to a lower version of the protocol are disclosed. The device detects a presence of a receiver, and starts link training. During the link training, the number of link training failures or the elapsed time is counted. The device transmits a training sequence including symbols set in accordance with a higher version of the protocol that the device supports on each lane that the receiver is detected as long as the number of link training failures or the elapsed time is below a predetermined threshold. If the number of link training failures or the elapsed time reaches a predetermined threshold, the device transmits a training sequence including symbols set in accordance with a lower version of the protocol.