PCIe Link Training Bypassing Equalization at Lower Data Rates
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Solution Overview
Problem
Current interconnect architectures face challenges in efficiently managing data rates and power consumption as computing systems evolve, particularly in high-performance computing environments where faster data transfer rates are needed without compromising power efficiency.
Innovation Solution
The implementation of a sequential equalization bypass mode in PCIe link training, which allows devices to bypass equalization at lower data rates and directly operate at the highest common data rate supported by all devices on the link, reducing latency and enabling quicker initial link training.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential equalization is performed at each data rate during PCIe link training, then link stability and signal integrity are improved, but link training time and latency increase
Solution Approach 1:
The patent applies the skipping principle by allowing the link training process to bypass equalization at lower data rates when the target data rate is significantly higher. Instead of performing equalization at every intermediate data rate, the system can skip directly to equalization at the target data rate, reducing training time while maintaining link stability when operating at high speeds.
Solution Approach 2:
The patent implements dynamics by making the equalization process adaptive based on the target data rate. The system dynamically determines whether to perform equalization at intermediate data rates or skip directly to the target rate, adjusting the training procedure based on operational conditions and requirements.
2Reliability
If equalization is performed at multiple data rates during link training, then compatibility and reliability are improved, but power consumption increases
Solution Approach 1:
The patent reduces power consumption by skipping equalization at lower data rates when transitioning to high data rates. This eliminates unnecessary power expenditure during intermediate training stages while maintaining link reliability through targeted equalization at the operational data rate.
Solution Approach 2:
The patent changes the operational parameters of the equalization process by adjusting the decision criteria for when to perform equalization. By modifying parameters such as the threshold for skipping equalization or the target data rate selection, the system optimizes the balance between reliability and power consumption.
3Productivity
If faster data rates are implemented in interconnect architectures, then system performance is improved, but power consumption and heat generation increase
Solution Approach 1:
The patent applies preliminary action by performing equalization at the target high data rate before actual data transmission begins. This preparatory equalization ensures the link is optimized for high-speed operation from the start, enabling faster data rates without excessive power consumption during the training phase.
Solution Approach 2:
The patent utilizes parameter changes by adjusting equalization parameters specifically for high data rate operation. By optimizing parameters such as equalization tap weights, timing recovery settings, and signal level thresholds for high-speed operation, the system achieves high productivity while controlling power consumption through precise parameter tuning.
Data Source
AI summary
A port of a computing device is to connect to another device over a link and use equalization logic to perform equalization of the link at a plurality of different data rates. The equalization logic may identify that the other device supports bypassing a sequential equalization mode, determine a maximum data rate supported by the devices on the link, and participate in equalization of the link at the maximum supported data rate before equalizing the link at one or more other data rates lower than the maximum supported data rate in the plurality of data rates.