PCIe LTSSM State Branching for Corner-Case Board Testing

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Solution Overview

Problem

Current analyzer devices are unable to test all corner cases covered by the PCI Express Link Training and Status State Machine (LTSSM) due to its complexity and adherence to specific rule sets, limiting the ability to evaluate different states of a PCI board.

Innovation Solution

A device is provided that generates a programmable LTSSM test configuration, allowing for tracing through various states and paths, modifying the configuration based on results, and enabling simulation of unexpected states and transitions to test corner cases.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a fixed LTSSM configuration is used for testing, then the testing process is simple and follows standard specifications, but the ability to test corner cases and unexpected states is limited

Engineering Contradiction:
Improvetesting capabilityVSAvoidtest configuration complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a dynamic test configuration system where the LTSSM state machine can be programmatically modified during runtime. The test configuration is no longer static but can adapt based on test results, allowing the system to explore corner cases and unexpected states while maintaining manageable complexity through structured modification approaches.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system allows modification of LTSSM configuration parameters such as state transition conditions, timing values, and state machine behavior. By changing these parameters dynamically based on test outcomes, the system achieves versatile testing capability without requiring complete redesign of the test framework, thus managing complexity.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If comprehensive testing of all LTSSM states is performed, then testing coverage is improved, but the time required for testing increases due to the need to modify configurations iteratively

Engineering Contradiction:
Improvetesting coverageVSAvoidtesting duration
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system implements feedback loops where test results from tracing through the LTSSM configuration are automatically analyzed, and the configuration is modified based on this feedback. This automated feedback mechanism enables comprehensive testing coverage without manual intervention for each configuration change, significantly reducing the time penalty that would otherwise accompany iterative testing.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system performs preliminary analysis of test results to determine which configuration modifications are needed before executing the next test phase. By preparing modification plans in advance based on previous test outcomes, the system minimizes idle time and ensures continuous progress toward comprehensive testing coverage.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250307099A1Peripheral component interconnect board programmable link training and status state machine and state branching
Publication Date: 2025.10.02 VIAVI SOLUTIONS INC(US)
  • US20250307099A1 patent drawing
  • US20250307099A1 patent drawing
  • US20250307099A1 patent drawing

AI summary

A device may generate a link training and status state machine (LTSSM) test configuration that includes states and paths connecting the states, and may provide the LTSSM test configuration for tracing through by a device under test. The device may receive results associated with tracing through of the LTSSM test configuration by the device under test, and may modify, based on the results, one of the paths of the LTSSM test configuration to include a different one of the states and to generate a modified LTSSM test configuration. The device may provide the modified LTSSM test configuration for tracing through by the device under test.