PCIe Memory Mapped Storage Controller Backend Architecture
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Solution Overview
Problem
Large storage systems using rotating media face latency issues in accessing data, and implementing higher level caches to pre-load data does not scale effectively due to limited controller memory, which restricts the capacity and performance of storage controllers.
Innovation Solution
A backend memory controller connected via PCIe to storage controllers, allowing additional memory to be mapped to storage controller memories, enabling the storage of data structures for a second-level cache without compromising controller performance, and providing expandable memory for processing functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If higher level caches of increasing size are implemented to pre-load data, then the volume of pre-loaded data increases, but the controller memory capacity is limited by circuit board space, restricting further cache expansion
Solution Approach 1:
The patent transitions from planar circuit board mounting to three-dimensional stacking architecture. Memory devices are stacked vertically above the controller chip using through-silicon via (TSV) technology, enabling memory capacity expansion in the vertical dimension rather than being constrained by horizontal circuit board area. This allows significantly larger cache capacities while maintaining the same footprint.
Solution Approach 2:
The patent implements a nested hierarchical structure where multiple memory devices are stacked and integrated around a central controller. The controller chip is positioned at the base, with memory devices stacked vertically above it, creating a nested configuration where the controller is embedded within the memory stack structure. This enables the controller to access memory through vertical interconnects rather than lateral connections.
2Quantity of substance
If larger caches are implemented, then more data can be pre-loaded, but data structures identifying data location must be maintained in controller memory, compromising controller performance
Solution Approach 1:
The patent divides the memory system into separate functional segments: the controller chip handles data processing and management operations, while the stacked memory devices store both data and metadata structures. By segmenting the memory space into data regions and metadata regions within the stacked memory, the controller can access metadata without bottlenecking its processing performance, while the large cache capacity is maintained in the vertical memory stack.
3Quantity of substance
If rotating storage media are used for mass storage, then economical storage solution is provided, but access speeds are considerably slower than electronic storage components
Solution Approach 1:
The patent implements a multi-level cache hierarchy using vertically stacked memory devices positioned between the controller and rotating storage media. Frequently accessed data is pre-loaded into this cache memory in advance of actual read requests, eliminating the need to access rotating media for every data operation. This preliminary caching action significantly reduces access latency while maintaining the economical rotating media for bulk storage capacity.
Data Source
AI summary
Systems and methods are provided for expanding the available memory of a storage controller. The systems and methods utilize a PCIe memory controller connected to the backend interface of the storage controller. Memory of the PCIe memory controller is memory mapped to controller memory of the storage controller. The PCIe connection allows the storage controller to access the memory of the PCIe memory controller with latencies similar to that of the controller memory.