PCI-E Memory Segmentation for CPU Bandwidth Optimization
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Solution Overview
Problem
In existing server systems, when multiple CPUs access data stored in a CPU's memory through a PCI-E bus, it leads to bandwidth occupation, reducing the utilization rate of CPUs as data access involves multiple buses, causing inefficiency.
Innovation Solution
The operating system configures address information for PCI-E devices to store data in a PCI-E memory, allowing a specific CPU to access and process the data, thereby avoiding unnecessary bandwidth occupation by optimizing data access paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If PCI-E devices store data in CPU memory, then data access is simplified, but bus bandwidth is occupied and CPU utilization rate decreases
Solution Approach 1:
The patent segments memory resources by introducing PCI-E memory as a separate memory space from CPU memory. PCI-E devices store data in PCI-E memory while CPUs access data in CPU memory, dividing the memory architecture into distinct segments that operate independently, thereby eliminating bus bandwidth conflicts and improving CPU utilization.
2Adaptability or versatility
If multiple CPUs access data through a single CPU's memory, then data sharing is enabled, but bus bandwidth between CPUs is occupied
Solution Approach 1:
The patent introduces PCI-E memory as an intermediary storage layer between PCI-E devices and multiple CPUs. Instead of multiple CPUs directly accessing a single CPU's memory through occupied bus bandwidth, the system uses PCI-E memory as a mediator that PCI-E devices can store data in, and CPUs can then access independently, reducing bus bandwidth consumption while maintaining data sharing capability.
Data Source
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AI summary
Embodiments of the present invention provide a data processing method and apparatus, a PCI-E bus system, and a server. The method includes: configuring address information of a PCI-E memory of a PCI-E device, so that the PCI-E device stores data received by the PCI-E device in the PCI-E memory; and controlling a CPU to access the data stored in the PCI-E memory, so that the CPU processes the data. In the embodiments of the present invention, a problem that in the prior art, because the PCI-E device stores the data received by the PCI-E device in a memory of the CPU, when the data stored in the memory of the CPU is accessed by another CPU, a part of a bandwidth of a bus between the another CPU and the CPU is occupied and a bus through which the CPU accesses the memory that corresponds the CPU is occupied can be avoided, thereby improving a utilization rate of the CPU.