PCIe-Linked Storage Message Passing for HPC Inter-Process Communication
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Solution Overview
Problem
Current compute infrastructure lacks efficient inter-process communication techniques for interdependent parallel processes, particularly in enterprise environments where High Performance Computing (HPC) workloads require synchronous execution, necessitating improved methods for message passing among multiple compute nodes.
Innovation Solution
Implementing message passing using a shared memory via Peripheral Component Interconnect Express (PCIe)-linked storage devices, allowing messages to be stored persistently and asynchronously, reducing duplication and latency by leveraging low-latency PCIe communications for inter-process communication among interdependent parallel processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional message logging schemes are used for inter-process communication, then messages can be transmitted between processes, but message duplication occurs and bandwidth requirements increase
Solution Approach 1:
The patent merges the message transmission path with the persistent storage path by having both the message buffer and persistent log reside in the same PCIe-addressable memory space. This eliminates the need for separate message copying operations, thereby removing message duplication and reducing bandwidth consumption while maintaining reliable message delivery between processes.
Solution Approach 2:
The PCIe-addressable memory space serves multiple functions simultaneously: it acts as both the message buffer for inter-process communication and the persistent log storage for fault tolerance. This multi-functionality eliminates the need for separate dedicated message queues and log storage, reducing overall bandwidth requirements while ensuring reliable message delivery.
2Reliability
If synchronous message passing is implemented for interdependent parallel processes, then processes can maintain synchronization, but latency increases
Solution Approach 1:
The patent implements preliminary action by pre-allocating message buffers and persistent log entries in the PCIe-addressable memory space before message passing occurs. Processes can directly access pre-prepared memory locations for sending and receiving messages, eliminating the need for dynamic memory allocation and reducing latency while maintaining synchronization through ordered memory access.
Solution Approach 2:
The PCIe-switch fabric acts as an intermediary that enables direct memory-to-memory message passing between processes on different compute nodes. This intermediary provides low-latency communication by bypassing traditional network stacks while maintaining synchronization through reliable delivery mechanisms, thereby reducing message passing latency without sacrificing process coordination.
3Productivity
If distinct compute sites are used for HPC and enterprise workloads, then each workload type can be optimized, but infrastructure complexity increases
Solution Approach 1:
The patent makes enterprise compute infrastructure universal by enabling HPC workloads to run on standard PCIe-based systems through direct access to PCIe-addressable persistent memory. This allows the same hardware platform to serve both enterprise applications and HPC workloads with interdependent parallel processes, eliminating the need for separate specialized HPC clusters and reducing overall infrastructure complexity.
Solution Approach 2:
The system enables self-service by allowing HPC processes to directly access and manage their own message buffers and persistent logs in PCIe-addressable memory without requiring specialized HPC hardware or complex interconnects. This self-service capability allows standard enterprise infrastructure to support HPC workloads, consolidating compute resources and reducing infrastructure complexity.
Data Source
AI summary
Message passing is provided among a plurality of interdependent parallel processes using a shared memory. Inter-process communication among a plurality of interdependent processes executing on a plurality of compute nodes is performed by obtaining a message from a first process for a second process; and storing the message in a memory location of a Peripheral Component Interconnect Express (PCIE)-linked storage device, wherein the second process reads the memory location to obtain the message. The message is optionally persistently stored in the PCIE-linked storage device for an asynchronous checkpoint until the message is no longer required for an asynchronous restart.