Converged PCIe M-PHY Protocol Stack for Low Power Mobile
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Solution Overview
Problem
Conventional load/store communication protocols like PCIe, designed for high performance without power efficiency considerations, do not scale down effectively for low power applications such as mobile devices, and existing link management schemes are complex due to multiple form factor requirements.
Innovation Solution
A protocol stack that combines a conventional PCIe protocol with a low power physical unit, such as M-PHY, to leverage legacy components while reducing power consumption, and includes optimized link training and management mechanisms, flow control, and a consolidated sideband mechanism for efficient communication in mobile devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional PCIe protocol is used for high performance communication, then communication speed and performance are improved, but power consumption increases and it does not scale down for mobile devices
Solution Approach 1:
The patent segments the communication protocol into two distinct parts: a high-performance protocol stack (PCIe) for data communication and a separate low-power physical layer (M-PHY) for signal transmission. This segmentation allows each layer to be optimized independently - the PCIe protocol maintains high-speed communication capabilities while the M-PHY physical layer reduces power consumption through efficient signal encoding and lower voltage operation, resolving the contradiction between speed and power usage in mobile devices.
2Adaptability or versatility
If existing link management schemes are implemented to support multiple form factors, then compatibility and adaptability are improved, but system complexity increases and transition processes lengthen
Solution Approach 1:
The patent implements a universal link management approach where the M-PHY physical layer and its associated link training mechanisms are designed to handle multiple form factors and communication scenarios through a single unified interface. The link training state machine and training sequences are configured to automatically adapt to different device types and connection configurations, eliminating the need for separate management schemes for each form factor. This universal design reduces complexity while maintaining compatibility across diverse device implementations.
3Reliability
If conventional PCIe link training mechanisms are used, then comprehensive device detection and configuration are achieved, but training time and power consumption during initialization increase
Solution Approach 1:
The patent applies preliminary action by implementing optimized link training sequences and state machines that perform essential device detection and configuration tasks more efficiently. The M-PHY link training mechanism includes pre-configured training patterns and accelerated detection algorithms that reduce the number of training iterations required compared to conventional PCIe mechanisms. This preliminary optimization maintains reliable device detection while significantly reducing the time and power consumed during the initialization phase, making it suitable for mobile devices with power and time constraints.
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AI summary
In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide for data transfer across a physical interconnect. This stack can be incorporated in an apparatus that includes a protocol stack for a first communication protocol including transaction and link layers, and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include a physical unit circuit according to the second communication protocol. Other embodiments are described and claimed.