PCIe CEM NIC Timing Sync via Repurposed JTAG Pins
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Solution Overview
Problem
Existing PCIe CEM NICs do not specify precision timing functions, requiring proprietary hardware or coaxial cables for timing synchronization, which are cumbersome and difficult to implement, and the PCIe CEM standard lacks pins for independent clock propagation.
Innovation Solution
Repurpose JTAG pins on PCIe CEM NICs for precision timing synchronization, using them as flexIO pins to transmit timing signals, eliminating the need for coaxial cables and enabling standardization of timing synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If proprietary hardware or coaxial cables are used for timing synchronization, then timing precision can be achieved, but device complexity and ease of operation deteriorate
Solution Approach 1:
The PCIe CEM connector pins are designed to serve multiple functions: data transmission and timing signal propagation. By integrating timing synchronization capability into the existing data connector, the patent eliminates the need for separate coaxial cables and proprietary hardware, thereby reducing device complexity while maintaining timing precision
Solution Approach 2:
The patent combines data transmission and timing synchronization functions into a single connector interface. The same PCIe CEM pins that carry data signals are also used to propagate timing clocks, merging two previously separate functions into one unified interface, which simplifies the overall system architecture
2Measurement precision
If coaxial cables are used for timing synchronization, then timing precision is maintained, but ease of operation and installation deteriorate
Solution Approach 1:
The PCIe CEM connector is designed to universally handle both data and timing signals through the same pins. This multi-functionality allows timing synchronization to be achieved through the existing data connection interface, eliminating the need for separate coaxial cable connections and making installation as simple as plugging in the standard PCIe card
3Measurement precision
If proprietary hardware is used for precision timing, then timing accuracy is achieved, but adaptability and standardization deteriorate
Solution Approach 1:
The patent makes timing synchronization a universal feature of standard PCIe CEM connectors by defining specific pin assignments for timing clock propagation. This allows any PCIe CEM-compliant NIC to support precision timing without requiring proprietary hardware, thereby achieving both timing accuracy and standardization compatibility
Solution Approach 2:
Instead of adding specialized proprietary hardware to achieve timing synchronization, the patent inverts the approach by utilizing the existing standard PCIe CEM connector infrastructure. The timing function is embedded within the standard connector specification, allowing standard hardware to achieve precision timing that previously required specialized equipment
Data Source
AI summary
Architectures and techniques are described that can facilitate precision timing synchronization with a network interface card (NIC) that is compliant with a peripheral component interconnect express (PCIe) card electromechanical (CEM) specification. In that regard, certain pins that are specified to provide JTAG functionality can be repurposed. Thereafter the particular JTAG pins that are repurposed for precision timing synchronization functions can be utilized to provide precision timing synchronization functions, USB functions, or both. Because the timing synchronization flows through the pins of the NIC, other cabling (e.g., coaxial cables) implemented for the express purpose of timing synchronization can be eliminated.