PCIe Controller with NVMe Interface and DRAM Caching
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Solution Overview
Problem
Current PCIe storage solutions face limitations in optimizing Input/Output (I/O) performance for flash memory devices like SSDs, as they lack efficient mechanisms for processing and caching data across persistent storage interfaces.
Innovation Solution
A PCIe controller configured with NVMe interfaces, incorporating a DRAM device partitioned into logical blocks, virtual function logic, and data buffers, which processes I/O requests, caches data, and transfers it efficiently between the host system and SSDs, utilizing firmware to streamline I/O operations and provide a virtual I/O interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional PCIe storage interfaces are used, then device compatibility is maintained, but I/O performance is limited
Solution Approach 1:
The patent segments the storage interface into two distinct layers: the transport layer (PCIe) and the logical interface layer (NVMe). This segmentation allows the PCIe bus to handle high-speed data transmission while the NVMe interface optimizes I/O operations specifically for flash memory devices, thereby improving I/O performance without compromising PCIe compatibility
Solution Approach 2:
The NVMe interface acts as an intermediary between the host system and flash memory devices, translating high-performance I/O operations into PCIe bus transactions. This intermediary layer enables optimized I/O paths while maintaining compatibility with the existing PCIe infrastructure
2Speed
If data is stored directly in flash memory, then persistent storage is achieved, but access speed is reduced
Solution Approach 1:
The patent introduces DRAM as an intermediary caching layer between the host system and flash memory devices. Frequently accessed data is cached in DRAM for rapid access, while the flash memory maintains persistent storage. This intermediary caching mechanism resolves the contradiction by providing both fast access speeds and data persistence
Solution Approach 2:
The system performs preliminary actions by pre-loading frequently accessed data into DRAM cache before it is actually needed. This anticipatory caching strategy ensures that when data is requested, it is already available in fast memory, thereby improving access speed while maintaining data persistence in the flash memory
3Productivity
If protocol overhead is reduced, then I/O efficiency is improved, but system compatibility is compromised
Solution Approach 1:
The patent segments the protocol stack to separate compatibility-handling functions from performance-optimization functions. The PCIe protocol layer maintains compatibility with existing systems, while the NVMe logical interface layer implements simplified, efficient protocols optimized for flash memory operations, thereby achieving both compatibility and efficiency
Data Source
AI summary
Systems and methods presented herein provide for SSD data storage via PCIe controllers configured with NVMe interfaces. In one embodiment, a PCIe controller includes a plurality of buffers, a Dynamic Random Access Memory (DRAM) device, and an I/O processor operable to partition the DRAM device into a plurality of logical blocks. The controller also includes virtual function logic communicatively coupled to the logical blocks of the DRAM device and to the buffers. The virtual function logic is coupled to a host system through the I/O processor to process an I/O request from the host system to a logical block of the DRAM device, to retrieve data from the logical block to at least one of the buffers, and to transfer the data from the buffer to the host system.