PCIe Interface System with NVMe Lightweight Notification

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Solution Overview

Problem

Current PCIe-based storage systems face inefficiencies in command fetching times due to non-DMA operations, which hinder input/output random performance.

Innovation Solution

Implementing a PCIe lightweight notification (LN) system that registers command positions in host memory and prefetches commands, allowing for quicker access and operation by NVMe devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If non-DMA operations are used for command fetching, then device complexity is reduced, but command fetching time increases and I/O random performance deteriorates

Engineering Contradiction:

Improvecommand fetching timeVSAvoidI/O random performance

Core Design Contradiction:

Loss of timeVSProductivity

Solution Approach 1:

The patent implements command prefetching by registering lightweight notifications (LN) at command positions in host memory before the NVMe device needs to fetch them. This preliminary action allows commands to be prepared and staged in advance, reducing the actual fetching time when the device needs to execute them, thereby improving I/O random performance without requiring complex DMA operations.

Inventive Principle:

Principle #10Preliminary action

2Loss of time

If lightweight notification registration is implemented, then command fetching time is reduced, but device complexity increases

Engineering Contradiction:

Improvecommand fetching timeVSAvoidPCIe interface system complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent introduces lightweight notifications (LN) as an intermediary mechanism between the host memory and the NVMe device. Instead of implementing complex DMA hardware or software, the LN serves as a simple notification system that records command positions in host memory, allowing the device to efficiently locate and fetch commands without requiring sophisticated memory management infrastructure.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Productivity

If command prefetching is enabled, then I/O random performance is enhanced, but memory usage increases

Engineering Contradiction:

ImproveI/O random performanceVSAvoidhost memory usage

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

The patent applies local quality by registering lightweight notifications only at specific command positions in host memory where prefetching is beneficial, rather than uniformly managing entire memory regions. This selective approach allows command prefetching to occur only where needed, improving I/O random performance while minimizing unnecessary memory consumption and maintaining efficient memory utilization.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS11789658B2Peripheral component interconnect express (PCIe) interface system and method of operating the same

Publication Date: 2023.10.17 SK HYNIX INC

AI summary

A peripheral component interconnect express (PCIe) interface system is provided to include a PCIe interface device, a host, and a non-volatile memory express (NVMe) device connected to the host through the interface device. The host includes a host memory configured to store information on a command to be executed on the NVMe device and a command that has been executed on the NVMe device, and an NVMe driver configured to transmit the command to be executed on the NVMe device to the host memory, and output a doorbell signal indicating that the command to be executed on the NVMe device has been stored in the host memory to the NVMe device. The NVMe device requests to the host memory to register a lightweight notification (LN) indicating a position in which the command to be executed on the NVMe device is stored.