PCIe NVMe Power Control via Dynamic Operation Stalling

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Solution Overview

Problem

Traditional methods for controlling power in PCIe direct attached non-volatile memory storage systems are inadequate, as they either shut down the system or negatively impact performance by not actively managing power consumption, especially when operations exceed the limited power supply capabilities of the PCIe interface.

Innovation Solution

A method that monitors the state of attached non-volatile memory, determines if new operations would exceed a preset power threshold, and stalls execution if necessary, while continuing existing operations, using a power control module to manage power supply, timing offsets, and a credit system to optimize power usage and prevent exceeding power limits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional power control methods are used (cutting off power or shutting down the system), then power limits are enforced, but system performance is negatively impacted and reliability decreases

Engineering Contradiction:
Improvesystem stabilityVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements dynamic power management by monitoring real-time power consumption of PCIe non-volatile memory devices and adjusting power supply accordingly. The system transitions from static power limits to dynamic control, allowing the power supply to adapt to varying operational demands while maintaining safety margins.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system continuously monitors power consumption levels from the non-volatile memory device and uses this feedback to determine when to stall operations. This closed-loop control ensures that power consumption remains within safe limits while maximizing performance, preventing the need for system shutdowns.

Inventive Principle:
Principle #23Feedback

2Speed

If power supply to PCIe memory is increased to support high-performance operations, then throughput and access rates improve, but the risk of exceeding safe power limits increases

Engineering Contradiction:
Improvedata access throughputVSAvoidpower limit violation risk
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The system performs preliminary monitoring of power consumption levels before allowing high-performance operations to proceed. By detecting power consumption trends in advance, the system can preemptively stall operations that would cause power limits to be exceeded, preventing harmful effects before they occur.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent dynamically adjusts operational parameters such as I/O rates and operation timing based on real-time power consumption measurements. When power consumption approaches safe limits, the system modifies these parameters to reduce power demand while maintaining acceptable performance levels.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If operations are stalled to manage power consumption, then power limits are enforced, but operation completion time increases

Engineering Contradiction:
Improvepower safetyVSAvoidoperation latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system implements periodic monitoring and evaluation of power consumption levels, allowing operations to proceed during safe windows and stalling only when necessary. This periodic control approach minimizes the impact of power management interventions on overall operation completion time.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The system applies partial stalling rather than complete operation cancellation when power limits are approached. By stalling only the portion of operations that would cause power violations while allowing other operations to continue, the system minimizes time loss while maintaining power safety.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10552284B2System and method for controlling PCIe direct attached nonvolatile memory storage subsystems
Publication Date: 2020.02.04 WESTERN DIGITAL TECHNOLOGIES INC
  • US10552284B2 patent drawing
  • US10552284B2 patent drawing
  • US10552284B2 patent drawing

AI summary

Techniques for controlling power on a PCIe direct attached non-volatile memory storage system are disclosed. In one particular embodiment, the techniques may be realized as a method for controlling power including providing power to a memory attached via the PCIe interface; monitoring a state of the attached memory; determining whether a new operation to be implemented on the attached memory would cause the power provided to the memory to exceed a preset threshold; and stalling execution of the new operation on the attached memory when it is determined that the new operation would exceed the preset threshold while continuing execution of preexisting operations on the attached memory.