PCIe OOB Handshake for Deterministic Link Training
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Solution Overview
Problem
PCIe link training in computer architectures is associated with timing inefficiencies and indeterministic behavior due to the inability of host systems to synchronize with the power-up state of compute-intensive PCIe cards, leading to delayed and non-deterministic link training and resource allocation.
Innovation Solution
Implementing a PCIe processor to monitor the state of the PCIe SOC device using out-of-band communication, such as an SMBus, to provide a dynamic handshake between the host processor and the PCIe card, ensuring deterministic link training and enumeration by periodically updating the host on the card's power-up and configuration status.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PCIe link training is performed using conventional in-band communication methods, then the PCIe protocol can be implemented, but timing inefficiencies and indeterministic behavior occur due to inability to synchronize with power-up state
Solution Approach 1:
The patent introduces an out-of-band communication channel (SMBus) as an intermediary between the host processor and PCIe device. This separate communication path allows the host to monitor the device's power-up state and configuration progress without interfering with the PCIe link training process, enabling deterministic timing by triggering link training only when the device is ready.
2Reliability
If the host system waits for PCIe card configuration completion before link training, then deterministic behavior is achieved, but processing time increases
Solution Approach 1:
The host processor performs preliminary monitoring of the PCIe device's configuration status through out-of-band communication during the device's power-up sequence. This allows the host to determine in advance when the device is ready for link training, avoiding both premature initiation (which would cause failures) and excessive waiting (which would reduce productivity).
Solution Approach 2:
The patent implements a feedback mechanism where the PCIe device periodically updates the host processor about its configuration status through the SMBus. This feedback loop enables the host to make informed decisions about when to initiate link training, achieving deterministic behavior without unnecessary delays.
3Reliability
If PCIe enumeration is performed on every power-up state transition, then resource allocation is ensured, but processing overhead increases
Solution Approach 1:
The patent applies partial enumeration by performing full PCIe resource allocation only when transitioning to higher power states (D3cold to D0, D3 to D0) where the device's configuration may have changed. For transitions within the same power state or to lower states, the system skips redundant enumeration steps, reducing processing overhead while maintaining resource allocation accuracy when necessary.
Data Source
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AI summary
A Peripheral Component Interface Express (PCIe) card includes a circuit board, a device mounted on the circuit board, and a PCIe processor mounted on the circuit board. The PCIe processor is communicatively coupled to the device and a host processor of a host system. The PCIe processor is configured to detect a power signal on an auxiliary (AUX) power rail of the PCIe card. A periodic detection of a state of the device is performed based on detecting the power signal on the AUX power rail. A signal indicative of the state of the device is encoded for transmission to the host processor of the host system. PCIe link training is performed via a PCIe interface with the host system. The PCIe link training is initiated based on the signal indicative of the state of the device.