PCIe Packet Buffering for Access Validation
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Solution Overview
Problem
In PCIe networks, existing solutions are bandwidth and latency intensive due to the need for transmitting packets to and from the root port for access validation, which can lead to malicious access violations and inefficiencies in communication.
Innovation Solution
A data processing apparatus with communication circuitry that buffers translated PCIe packets until permission checks are completed, reducing the need for packet transmission to the root port by using permission check packets to verify access permissions, thereby saving bandwidth and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If translated PCIe packets are transmitted to the root port for access validation, then security and access control are ensured, but bandwidth consumption increases and latency increases
Solution Approach 1:
The patent segments the packet transmission process into two independent parts: a permission check packet (header only) and the actual data packet. The permission check is performed separately using a simplified packet structure, allowing the full data packet to be buffered locally without being transmitted to the root port, thus reducing bandwidth consumption while maintaining security validation.
Solution Approach 2:
The patent extracts the permission checking function from the full packet transmission process. By using a separate permission check packet that contains only essential header information, the system separates the security validation task from the data transfer task, enabling the data packet to be handled locally without unnecessary transmission to the root port.
2Reliability
If translated PCIe packets are transmitted to the root port for access validation, then security and access control are ensured, but latency increases
Solution Approach 1:
The patent segments the validation process from the data transfer process. The permission check packet is processed independently and quickly, allowing the system to make access decisions without waiting for the full data packet to be transmitted to the root port, thereby reducing latency while maintaining security validation.
Solution Approach 2:
The patent performs preliminary permission checking using a simplified packet structure before the actual data transfer. By validating access rights in advance using the permission check packet, the system avoids the latency penalty of transmitting the entire data packet to the root port for validation.
3Loss of energy
If permission check packets are used instead of transmitting full packets to root port, then bandwidth is reduced, but device complexity increases
Solution Approach 1:
The patent makes the data processing apparatus multi-functional by enabling it to perform both local packet buffering and permission checking. The same apparatus that receives and buffers translated packets also generates and processes permission check packets, consolidating multiple functions in one device rather than requiring separate dedicated components.
Solution Approach 2:
The patent introduces a permission check packet as an intermediary structure between the data processing apparatus and the root port. This intermediary carries only the essential permission information needed for validation, simplifying the communication protocol by using a standardized intermediate format that bridges local buffering needs with remote validation requirements.
Data Source
Figure 1
Figure 2
Figure 3A
AI summary
A data processing apparatus (100) is provided, that includes communication configured for receiving, from an origin Peripheral Component Interconnect Express (PCIe) device (210), a translated PCIe packet (A) comprising a destination field that comprises a physical address of a destination PCIe device (220). Permission circuitry transmits a permission check packet (C), separate to the translated PCIe packet (A), to a root port (230) to determine whether the origin PCIe device (210) has permission to access the destination PCIe device (220). Buffer circuitry (140) stores the translated PCIe packet (A) until a response (D) to the permission check packet (C) is received.