PCIe Packet Header Compression for Bus Throughput Efficiency
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Solution Overview
Problem
Conventional PCIe systems experience reduced bus throughput efficiency due to large packet headers in read completion and memory write request packets, which consume significant bus bandwidth.
Innovation Solution
The method involves generating read completion and memory write request packets with header portions less than 20 bytes, optimizing the Transaction Layer Packet (TLP) sequence number and completion tag to reduce packet size and improve transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional packet headers are used in PCIe communication, then complete information can be transmitted, but bus bandwidth is consumed excessively and throughput efficiency is reduced
Solution Approach 1:
The patent extracts and removes redundant header fields from PCIe packets. Specifically, it eliminates the need for certain address fields, tag fields, and other header components by implementing a simplified header structure that achieves the same communication objectives with fewer bytes, directly reducing packet overhead and increasing effective bus throughput
Solution Approach 2:
The patent changes the parameter of header length from the conventional 20 bytes to a reduced size. By modifying the header structure parameters (removing unnecessary fields, compressing address representations), the patent achieves shorter packet headers that consume less bus bandwidth while maintaining functional completeness
2Speed
If larger packet headers are transmitted, then more information is available for processing, but transmission time increases and bus utilization decreases
Solution Approach 1:
The patent segments the packet information by separating essential header data from optional or redundant data. By dividing the information into core necessary elements only, the patent creates a streamlined header structure that transmits only what is absolutely required, reducing transmission time without losing critical processing information
3Reliability
If conventional header structures are used, then all necessary information is included, but packet overhead increases and bandwidth efficiency decreases
Solution Approach 1:
The patent applies partial action by including only the necessary portion of header information rather than all possible fields. By transmitting a subset of header data that is sufficient for correct packet processing and routing, the patent achieves information completeness for operational reliability while minimizing bandwidth consumption
Data Source
AI summary
A computer system that employs Peripheral Component Interconnect Express (PCIe) links includes devices that generate a PCIe packet having a header portion that is smaller than the header portion for a conventional PCI packet. The devices may be an endpoint device, such as a graphics processor, and a chipset, such as a root-complex. The reduced size header improves the bus throughput efficiency of the computer system and reduces power requirements for the computer system.