PCIe Packet Ordering via Pointer-Based Mechanism
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Solution Overview
Problem
In PCI Express (PCIe) serial bus expansion bus controllers, maintaining the order of posted and completion transaction layer packets (TLPs) across multiple clock cycles is challenging due to the complexity of identification-based ordering and the potential for multiple TLPs to arrive simultaneously, which complicates error filtering and flow control.
Innovation Solution
A method and system for handling multiple packets using a pointer-based and identification-based ordering mechanism, where ordering tokens associate requester and virtual channel IDs with completion TLPs, allowing for efficient determination of the order of handling posted and completion TLPs without introducing additional attributes, and utilizing existing buffer structures for silicon area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If identification-based ordering mechanism is used to maintain TLP order, then ordering accuracy is improved, but device complexity increases due to tracking multiple IDs and VC IDs
Solution Approach 1:
The patent introduces ordering tokens as intermediary data structures that consolidate multiple tracking requirements (requester ID, completer ID, VC ID, pointer) into a single manageable object. These tokens act as mediators between the complex identification-based ordering requirements and the simpler pointer-based comparison mechanism, reducing the overall system complexity while maintaining ordering accuracy.
Solution Approach 2:
The ordering token structure serves multiple functions simultaneously: it stores identification information for matching, maintains pointer values for ordering comparison, and enables both identification-based and pointer-based ordering mechanisms. This multi-functionality reduces the need for separate data structures for each tracking requirement, thereby reducing device complexity.
2Productivity
If multiple TLPs are handled in a single clock cycle, then productivity is improved, but device complexity increases due to maintaining order among simultaneous packets
Solution Approach 1:
The patent replaces complex mechanical ordering mechanisms (comparing multiple IDs and VC IDs for every packet) with a simpler pointer-based comparison system. By substituting the identification-based ordering mechanism with pointer arithmetic and comparison, the system can handle multiple TLPs per clock cycle with reduced complexity, as pointer comparison is computationally simpler than multi-field identification matching.
Solution Approach 2:
The patent changes the ordering parameter from complex multi-field identification data to simple pointer values. This parameter transformation enables faster comparison operations that can be performed in parallel, allowing multiple TLPs to be ordered and handled in a single clock cycle without proportionally increasing device complexity.
3Device complexity
If pointer-based ordering mechanism is used, then device complexity is reduced, but measurement precision may be affected compared to identification-based ordering
Solution Approach 1:
The patent merges the identification-based ordering mechanism and pointer-based ordering mechanism into a unified hybrid approach. The system first uses identification-based ordering to establish initial packet order, then uses pointer-based ordering to maintain and refine this order during processing. This combination leverages the accuracy of identification matching while benefiting from the simplicity of pointer comparison, achieving both precision and low complexity.
Solution Approach 2:
The patent performs preliminary identification-based ordering before switching to pointer-based ordering. By establishing the correct order upfront using accurate identification matching, subsequent pointer-based operations can maintain this order without needing to perform complex comparisons, thus preserving measurement precision while reducing ongoing device complexity.
4Measurement precision
If additional attributes are introduced for ordering tokens, then ordering precision is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent extracts the essential ordering information from complex multi-field identification data and consolidates it into pointer values within ordering tokens. By taking out only the critical ordering parameter (pointer position) while retaining necessary identification fields, the system achieves high ordering precision without requiring extremely precise matching of multiple attributes, thereby reducing manufacturing precision requirements.
Data Source
AI summary
Disclosed are peripheral component interconnect (PCI) implementations and methods for implementing PCI implementations handling posted transaction layer packets (TLPs) and completion TLPs. PCI implementations include one or more receive buffers storing completion TLPs and posted TLPs, a set of write and read pointers for the receive buffers, a token manager to associate ordering tokens with posted TLPs, and a pointer-based ordering mechanism to determine an order for handling posted and completion TLPs. PCI implementations may further include an identification-based ordering mechanism to revise the order. The methods identify a completion TLP and multiple posted TLPs, associate a posted TLP with an ordering token, and determine the order for handling the completion and posted TLPs with at least the pointer-based ordering mechanism. The methods may further optionally revise the order with at least the identification-based ordering mechanism.