PCIe PHY Lane Disabling via Unconnected Power States
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Solution Overview
Problem
Existing power state change operations in lanes of NVMe SSDs over PCIe result in performance degradation and increased latency due to inefficient power saving levels, particularly when lanes are unconnected or unused.
Innovation Solution
Implementing an unactive lane controller (ULC) that uses side-band signaling to transition unused lanes into an unconnected power state, rather than an unused power state, to conserve current during low power modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If lanes are placed in unused power state, then exit latency is reduced, but power saving level is only medium
Solution Approach 1:
The patent changes the power state parameter of lanes from 'unused' to 'unconnected' state. This parameter change allows the system to achieve both low exit latency and high power saving by transitioning lanes to an unconnected power state rather than keeping them in unused state, thereby resolving the contradiction between exit latency and power saving level
2Loss of time
If lanes are kept in active state, then exit latency is minimized, but power consumption increases
Solution Approach 1:
The patent implements dynamic power state management for lanes through the ULC, which can transition lanes between active, unused, and unconnected states based on actual usage requirements. This dynamic approach allows the system to minimize power consumption during low power states while maintaining the capability to quickly activate lanes when needed, thereby resolving the contradiction between exit latency and power consumption
3Device complexity
If ULC controls multiple lanes, then device complexity is reduced, but control precision may decrease
Solution Approach 1:
The ULC is designed with multi-functionality to control multiple lanes simultaneously. It can operate in two modes: controlling multiple lanes together or controlling individual lanes independently. This universal design allows a single controller to handle various lane configurations and power state transitions, reducing device complexity while maintaining adequate control precision through its ability to adapt to different control granularities
Data Source
AI summary
Instead of entering lanes into an unused power state, enter unactive lanes into an unconnected power state to save more current during low power states. Using a small control logic will allow a controller to control unactive lanes in low power mode. When a lane is in an unactive power state or in an unused power state, an unactive lane controller (ULC) uses side-band signaling to place the unactive lane into either unused power state or unconnected power state. When a lane is in unused power state, then the ULC places the lane in unconnected power state. A single ULC is able to controller multiple lanes or you can have multiple ULC's, each controlling a single lane.