PCIe PHY Width Conversion for Cross-Generation Link Compatibility
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As computing systems become more complex, the interconnect architecture to couple and communicate between components also increases in complexity to meet bandwidth requirements, with different market segments demanding varying aspects such as higher performance in servers and power savings in mobile ecosystems, while existing interconnect technologies like PCIe face challenges in adopting new generations quickly.
Innovation Solution
A width and frequency converter (WFC) logic is implemented to connect devices with different link widths and frequencies, using hardware, software, or a combination of both, to facilitate communication between devices by converting link widths and frequencies, such as from 2x16 Gen 4 to 2x8 Gen 5 or vice versa, while preserving the connectivity and symbol placement rules of the underlying interconnect protocol like PCIe.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If devices use different generations of interconnect protocols to meet varying performance and power requirements, then adaptability is improved, but device complexity increases
Solution Approach 1:
A width and frequency converter is introduced as an intermediary device between PCIe devices operating at different link widths and frequencies. The converter includes a first interface for receiving data at a first link width and frequency, and a second interface for transmitting data at a second link width and frequency, enabling protocol compatibility without requiring complex multi-protocol support in each device
Solution Approach 2:
The width and frequency converter dynamically changes the parameters of data transmission by adjusting link width (number of lanes) and frequency (data rate) based on the capabilities of connected devices. This allows the system to adapt between different PCIe generations (e.g., Gen3 to Gen5) by modifying transmission parameters rather than requiring fixed protocol support
2Productivity
If link width is increased to achieve higher bandwidth, then data transmission capacity is improved, but device complexity and power consumption increase
Solution Approach 1:
The system dynamically adjusts link width based on the capabilities and requirements of connected devices. The width and frequency converter can operate at different link widths (e.g., x16, x8, x4) and frequencies (e.g., 2.5 GT/s, 5 GT/s, 16 GT/s) depending on the PCIe generation supported by the devices, allowing bandwidth optimization without fixed high-complexity configuration
Solution Approach 2:
The data transmission is segmented across multiple lanes that can be independently configured. The width and frequency converter divides the data stream across different numbers of lanes (link widths) depending on device capabilities, allowing flexible bandwidth adjustment without requiring all devices to support the maximum link width
3Speed
If new PCIe generations are adopted to increase data rates, then transmission speed is improved, but compatibility with existing devices deteriorates
Solution Approach 1:
The width and frequency converter serves as a mediator between newer PCIe generations (Gen4, Gen5) and older generations (Gen3). It receives high-speed data from Gen5 devices and converts it to lower speeds compatible with Gen3 devices, enabling protocol compatibility while preserving high data rates for devices that support them
Solution Approach 2:
The converter dynamically adjusts the data rate and frequency based on the capabilities of connected devices. It can operate at 2.5 GT/s for Gen3 compatibility, 5 GT/s for Gen4, and 16 GT/s for Gen5, allowing the system to achieve high transmission speeds where possible while maintaining backward compatibility
Data Source
AI summary
A system and apparatus can include a first port configured to support a first link width; a second port configured to support a second link width, the second link width different from the first link width; and physical layer logic to receive from the first port a first data block arranged according to the first link width and frequency; create at least one second data block arranged according the second link width and frequency, the at least one second data block including data bytes from the first data block arranged sequentially in the at least one second data block; and transmit the at least one second data block to the second port.