PCIe PHY Width and Frequency Conversion Across Link Generations
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Solution Overview
Problem
As computing systems become more complex, the interconnect architecture to couple and communicate between components also increases in complexity to meet bandwidth requirements, but existing interconnect protocols like PCIe struggle to efficiently transition between different generations, such as PCIe Gen 4 and Gen 5, leading to limitations in data rates and lane widths, especially for devices using older protocols.
Innovation Solution
A width and frequency converter (WFC) logic is implemented in hardware, software, or a combination of both, to connect devices with different link widths and frequencies, using PHY layer devices to perform conversions such as x16 to x8 or vice versa, while preserving symbol placement rules and supporting protocols like PCIe, thereby enabling efficient data transmission across different generations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If existing interconnect protocols like PCIe are used to connect devices, then device compatibility is maintained, but data rates and bandwidth are limited when transitioning between different generations
Solution Approach 1:
A width and frequency converter (WFC) device is introduced as an intermediary component between PCIe devices of different generations. The WFC includes a first PHY layer device that receives signals from a first PCIe device and a second PHY layer device that transmits signals to a second PCIe device, enabling seamless communication between devices operating at different data rates and link widths without requiring protocol changes in the end devices themselves.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting link width and frequency parameters in the PHY layer. The converter can transform link configurations such as converting between different lane widths (e.g., x16 to x8) and frequency rates (e.g., PCIe Gen 4 to Gen 5), allowing the interconnect to adapt to different generation requirements while maintaining protocol compatibility at the transaction layer.
2Quantity of substance
If link width is increased to meet bandwidth requirements, then data transmission capacity improves, but physical complexity and lane management become more difficult
Solution Approach 1:
The patent segments the high-speed data transmission function into separate components: the WFC handles the complex width and frequency conversion at the PHY layer, while the transaction layer devices maintain their original simpler interfaces. This segmentation allows bandwidth to be increased through link width aggregation without proportionally increasing the complexity of each individual device, as the conversion logic is centralized in the WFC.
3Speed
If frequency is increased to achieve higher data rates, then transmission speed improves, but signal integrity and interference become more problematic
Solution Approach 1:
The WFC acts as a signal intermediary that receives high-frequency signals from Gen 5 devices and converts them to lower-frequency signals compatible with Gen 4 devices. This frequency conversion in the PHY layer eliminates signal integrity issues and interference problems that would otherwise affect devices attempting to operate at incompatible frequencies, while still enabling high data rates through the conversion process.
Data Source
AI summary
A system and apparatus can include a first port configured to support a first link width; a second port configured to support a second link width, the second link width different from the first link width; and physical layer logic to receive from the first port a first data block arranged according to the first link width and frequency; create at least one second data block arranged according the second link width and frequency, the at least one second data block including data bytes from the first data block arranged sequentially in the at least one second data block; and transmit the at least one second data block to the second port.


