PCIe Port Power Gating via CLKREQ# Signal Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a tradeoff between power saving and performance in electronic devices, where reducing power consumption often sacrifices performance, and existing technologies struggle to optimize power management in processor environments, particularly in PCIe ports, leading to inefficiencies in power gating and communication states.
Innovation Solution
The implementation of a power gating capability for unpopulated hot plug capable PCIe ports, utilizing the CLKREQ# signal to detect hot plug events and enable dynamic squelch disable and mPHY power gating, allowing for reduced power consumption without performance loss, especially in mobile devices and docking scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power gating is applied to PCIe ports to reduce power consumption, then energy dissipation is reduced, but performance may be compromised due to potential latency in power state transitions
Solution Approach 1:
The patent implements dynamic power management by transitioning PCIe ports between active and power-saving states based on real-time hot plug detection. The system dynamically adjusts power gating status according to whether a device is detected or not, optimizing the balance between power consumption and performance requirements.
Solution Approach 2:
The system uses hot plug detection mechanisms to monitor the status of PCIe ports and provides feedback to the power management logic. This feedback loop enables the system to automatically adjust power gating states based on actual device presence, ensuring performance is maintained when needed while saving power when devices are absent.
2Loss of energy
If squelch functions are disabled to enable power gating, then power consumption is reduced, but detection capability for hot plug events may be compromised
Solution Approach 1:
The patent extracts and separates the hot plug detection function from the squelch mechanism. By using the CLKREQ# signal as a dedicated trigger for hot plug detection, the system can disable squelch functions for power saving while maintaining separate detection capability through the clock request signal, resolving the contradiction between power gating and detection accuracy.
3Loss of energy
If power gating is implemented for unpopulated ports, then energy dissipation is reduced, but system complexity increases due to additional power management logic
Solution Approach 1:
The patent makes the power management logic universal by using the existing CLKREQ# signal for multiple purposes: both as a normal operation signal and as a trigger for hot plug detection and power gating. This multi-functionality reduces the need for separate dedicated circuits, thereby limiting the increase in system complexity while achieving energy savings.
Data Source
AI summary
Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.